dtsmg.v

来自「用verilog HDL编写的基于fpga的动态数码管显示程序。」· Verilog 代码 · 共 43 行

module dtsmg(main_clk,rst,datain,bcd_led,ledcom,com_clk);
	input main_clk,rst;
	input [7:0] datain;
	output [1:0] com_clk;
	output [3:0] ledcom;
	output [3:0] bcd_led;
	
	reg [3:0] ledcom,bcd_led;
	//reg [3:0] dataout;
	reg [1:0] com_clk;
	
	always@(posedge main_clk)
		begin
			if(!rst||com_clk==3)com_clk<=0;
				else com_clk<=com_clk+1;
		end
	
	always@(com_clk)
		begin
			case(com_clk)
				2'b00:ledcom=4'b1110;
				2'b01:ledcom=4'b1101;
				2'b10:ledcom=4'b1011;
				2'b11:ledcom=4'b0111;
			endcase
		end
		
		
	always@(com_clk or datain)
		begin 
			case(com_clk)
				2'b00:bcd_led=datain[3:0];
				2'b01:bcd_led=datain[7:4];
				default:bcd_led=4'b0000;
			endcase
		end
endmodule