integerdiv.tan.rpt

一个任意整数分频程序,采用VHDL语言编写

; N/A           ; None        ; -10.300 ns ; q[1] ; lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk      ;
; N/A           ; None        ; -10.400 ns ; q[0] ; lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clk      ;
; N/A           ; None        ; -10.400 ns ; q[0] ; lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk      ;
; N/A           ; None        ; -10.400 ns ; q[0] ; lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk      ;
; N/A           ; None        ; -10.400 ns ; q[0] ; lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk      ;
; N/A           ; None        ; -11.400 ns ; q[3] ; lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[1] ; clk      ;
; N/A           ; None        ; -11.400 ns ; q[3] ; lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[0] ; clk      ;
; N/A           ; None        ; -11.400 ns ; q[3] ; lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[3] ; clk      ;
; N/A           ; None        ; -11.400 ns ; q[3] ; lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[2] ; clk      ;
; N/A           ; None        ; -11.700 ns ; q[3] ; lpm_counter:count1_rtl_1|alt_counter_f10ke:wysi_counter|q[3] ; clk      ;
; N/A           ; None        ; -11.700 ns ; q[3] ; lpm_counter:count1_rtl_1|alt_counter_f10ke:wysi_counter|q[2] ; clk      ;
; N/A           ; None        ; -11.700 ns ; q[3] ; lpm_counter:count1_rtl_1|alt_counter_f10ke:wysi_counter|q[1] ; clk      ;
; N/A           ; None        ; -11.700 ns ; q[3] ; lpm_counter:count1_rtl_1|alt_counter_f10ke:wysi_counter|q[0] ; clk      ;
+---------------+-------------+------------+------+--------------------------------------------------------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 6.0 Build 178 04/27/2006 SJ Full Version
    Info: Processing started: Tue Apr 21 20:19:16 2009
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off integerdiv -c integerdiv
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 158.73 MHz between source register "lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" and destination register "lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[1]" (period= 6.3 ns)
    Info: + Longest register to register delay is 5.200 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_F3; Fanout = 4; REG Node = 'lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: 2: + IC(0.300 ns) + CELL(1.700 ns) = 2.000 ns; Loc. = LC3_F3; Fanout = 1; COMB Node = 'Equal1~174'
        Info: 3: + IC(0.300 ns) + CELL(1.600 ns) = 3.900 ns; Loc. = LC8_F3; Fanout = 6; COMB Node = 'Equal1~175'
        Info: 4: + IC(0.300 ns) + CELL(1.000 ns) = 5.200 ns; Loc. = LC5_F3; Fanout = 5; REG Node = 'lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[1]'
        Info: Total cell delay = 4.300 ns ( 82.69 % )
        Info: Total interconnect delay = 0.900 ns ( 17.31 % )
    Info: - Smallest clock skew is 0.000 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 12; CLK Node = 'clk'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC5_F3; Fanout = 5; REG Node = 'lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[1]'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
        Info: - Longest clock path from clock "clk" to source register is 2.400 ns
            Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 12; CLK Node = 'clk'
            Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_F3; Fanout = 4; REG Node = 'lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
            Info: Total cell delay = 2.000 ns ( 83.33 % )
            Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Micro setup delay of destination is 0.600 ns
Info: tsu for register "lpm_counter:count1_rtl_1|alt_counter_f10ke:wysi_counter|q[3]" (data pin = "q[0]", clock pin = "clk") is 13.800 ns
    Info: + Longest pin to register delay is 15.600 ns
        Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_8; Fanout = 6; PIN Node = 'q[0]'
        Info: 2: + IC(4.500 ns) + CELL(1.600 ns) = 11.000 ns; Loc. = LC1_F2; Fanout = 2; COMB Node = 'Add0~72'
        Info: 3: + IC(1.600 ns) + CELL(1.700 ns) = 14.300 ns; Loc. = LC8_F8; Fanout = 5; COMB Node = 'Equal0~185'
        Info: 4: + IC(0.300 ns) + CELL(1.000 ns) = 15.600 ns; Loc. = LC6_F8; Fanout = 3; REG Node = 'lpm_counter:count1_rtl_1|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 9.200 ns ( 58.97 % )
        Info: Total interconnect delay = 6.400 ns ( 41.03 % )
    Info: + Micro setup delay of destination is 0.600 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 12; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_F8; Fanout = 3; REG Node = 'lpm_counter:count1_rtl_1|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
Info: tco from clock "clk" to destination pin "clk_out" through register "lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[0]" is 18.300 ns
    Info: + Longest clock path from clock "clk" to source register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 12; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC4_F3; Fanout = 4; REG Node = 'lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro clock to output delay of source is 0.500 ns
    Info: + Longest register to pin delay is 15.400 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC4_F3; Fanout = 4; REG Node = 'lpm_counter:count2_rtl_0|alt_counter_f10ke:wysi_counter|q[0]'
        Info: 2: + IC(1.300 ns) + CELL(1.100 ns) = 2.400 ns; Loc. = LC5_F2; Fanout = 1; COMB Node = 'temp~607'
        Info: 3: + IC(0.000 ns) + CELL(1.600 ns) = 4.000 ns; Loc. = LC6_F2; Fanout = 1; COMB Node = 'temp~597'
        Info: 4: + IC(0.300 ns) + CELL(0.800 ns) = 5.100 ns; Loc. = LC2_F2; Fanout = 1; COMB Node = 'temp~603'
        Info: 5: + IC(0.000 ns) + CELL(1.600 ns) = 6.700 ns; Loc. = LC3_F2; Fanout = 1; COMB Node = 'temp~596'
        Info: 6: + IC(0.300 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC7_F2; Fanout = 1; COMB Node = 'clk_out~2'
        Info: 7: + IC(0.700 ns) + CELL(6.300 ns) = 15.400 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'clk_out'
        Info: Total cell delay = 12.800 ns ( 83.12 % )
        Info: Total interconnect delay = 2.600 ns ( 16.88 % )
Info: Longest tpd from source pin "q[1]" to destination pin "clk_out" is 23.600 ns
    Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_9; Fanout = 10; PIN Node = 'q[1]'
    Info: 2: + IC(4.500 ns) + CELL(1.600 ns) = 11.000 ns; Loc. = LC1_F3; Fanout = 1; COMB Node = 'temp~586'
    Info: 3: + IC(1.300 ns) + CELL(1.000 ns) = 13.300 ns; Loc. = LC2_F2; Fanout = 1; COMB Node = 'temp~603'
    Info: 4: + IC(0.000 ns) + CELL(1.600 ns) = 14.900 ns; Loc. = LC3_F2; Fanout = 1; COMB Node = 'temp~596'
    Info: 5: + IC(0.300 ns) + CELL(1.400 ns) = 16.600 ns; Loc. = LC7_F2; Fanout = 1; COMB Node = 'clk_out~2'
    Info: 6: + IC(0.700 ns) + CELL(6.300 ns) = 23.600 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'clk_out'
    Info: Total cell delay = 16.800 ns ( 71.19 % )
    Info: Total interconnect delay = 6.800 ns ( 28.81 % )
Info: th for register "lpm_counter:count1_rtl_1|alt_counter_f10ke:wysi_counter|q[3]" (data pin = "q[1]", clock pin = "clk") is -10.200 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.400 ns
        Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_126; Fanout = 12; CLK Node = 'clk'
        Info: 2: + IC(0.400 ns) + CELL(0.000 ns) = 2.400 ns; Loc. = LC6_F8; Fanout = 3; REG Node = 'lpm_counter:count1_rtl_1|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 2.000 ns ( 83.33 % )
        Info: Total interconnect delay = 0.400 ns ( 16.67 % )
    Info: + Micro hold delay of destination is 1.300 ns
    Info: - Shortest pin to register delay is 13.900 ns
        Info: 1: + IC(0.000 ns) + CELL(4.900 ns) = 4.900 ns; Loc. = PIN_9; Fanout = 10; PIN Node = 'q[1]'
        Info: 2: + IC(4.400 ns) + CELL(1.600 ns) = 10.900 ns; Loc. = LC1_F8; Fanout = 1; COMB Node = 'Equal0~183'
        Info: 3: + IC(0.300 ns) + CELL(1.400 ns) = 12.600 ns; Loc. = LC8_F8; Fanout = 5; COMB Node = 'Equal0~185'
        Info: 4: + IC(0.300 ns) + CELL(1.000 ns) = 13.900 ns; Loc. = LC6_F8; Fanout = 3; REG Node = 'lpm_counter:count1_rtl_1|alt_counter_f10ke:wysi_counter|q[3]'
        Info: Total cell delay = 8.900 ns ( 64.03 % )
        Info: Total interconnect delay = 5.000 ns ( 35.97 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning
    Info: Processing ended: Tue Apr 21 20:19:16 2009
    Info: Elapsed time: 00:00:01