integerdiv.vhd

来自「一个任意整数分频程序,采用VHDL语言编写」· VHDL 代码 · 共 47 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity integerdiv is
port(
clk:in std_logic;
q: in std_logic_vector(3 downto 0);
clk_out:out std_logic);
end entity integerdiv;
architecture one of integerdiv is
signal count1,count2:std_logic_vector(3 downto 0);
signal temp:std_logic;
signal n : integer range 0 to 100;
begin
n <=conv_integer(q);
process(clk)
begin
if clk'event and clk='1' then
  if count1=q-1 then count1<="0000";
   else count1<=count1+1;
   end if;
end if;
end process;
process(clk)
begin
if clk'event and clk='0' then
   if count2=q-1 then count2<="0000";
else
count2<=count2+1;
end if;
end if;
end process;
process(count1,count2)
begin
 if n>=2 then
   if (n mod 2)=1 then
     if count1<=((n / 2)-1)or  count2=((n/2)-1)  then temp<='1' ;else temp<='0';
     end if ;
     else if count1<=(n/2-1) then temp<='1' ;else temp<='0';
     end if;
    end if;
 else temp<=clk;
 end if;
end process;
clk_out<=temp;
end architecture one;