yima.rpt
来自「本源码用VHDL语言实现了用键盘控制米字管显示十进制」· RPT 代码 · 共 855 行 · 第 1/3 页
RPT
855 行
- 6 - A 15 AND2 3 1 0 5 :206
- 2 - A 14 AND2 3 1 0 5 :216
- 8 - A 18 AND2 3 1 0 5 :226
- 4 - A 14 AND2 3 1 0 3 :236
- 6 - A 18 AND2 3 1 0 3 :246
- 5 - A 19 OR2 0 3 0 1 :282
- 3 - A 22 OR2 s 0 3 0 2 ~328~1
- 6 - A 13 OR2 s 0 3 0 1 ~328~2
- 3 - A 16 OR2 s 0 2 0 5 ~346~1
- 8 - A 13 OR2 0 4 1 0 :346
- 8 - A 19 AND2 ! 0 2 0 1 :361
- 7 - A 16 OR2 0 4 0 1 :367
- 8 - A 16 OR2 0 4 0 1 :387
- 6 - A 16 AND2 s ! 0 2 0 2 ~391~1
- 1 - A 16 OR2 0 4 1 0 :397
- 7 - A 19 OR2 0 4 0 2 :412
- 1 - A 19 OR2 0 4 0 1 :426
- 1 - A 22 OR2 0 4 0 1 :441
- 7 - A 13 OR2 0 4 1 0 :448
- 4 - A 19 OR2 0 4 0 1 :471
- 4 - A 22 OR2 s 1 3 0 3 ~487~1
- 5 - A 13 OR2 s 0 3 0 1 ~487~2
- 1 - A 13 OR2 0 4 1 0 :499
- 3 - A 19 OR2 0 4 0 1 :517
- 5 - A 22 OR2 s 0 2 0 1 ~529~1
- 6 - A 22 OR2 0 4 0 1 :529
- 8 - A 22 OR2 0 4 0 1 :538
- 2 - A 22 OR2 0 3 1 0 :550
- 5 - A 15 OR2 1 3 0 1 :588
- 2 - A 16 OR2 0 4 1 0 :601
- 6 - A 19 OR2 s 0 3 0 2 ~628~1
- 2 - A 19 OR2 0 3 0 2 :628
- 8 - A 15 OR2 0 3 0 1 :640
- 2 - A 13 AND2 s 0 2 0 4 ~651~1
- 5 - A 16 OR2 0 4 1 0 :654
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: e:\juzhenjianpan\yima.rpt
yima
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 9/ 96( 9%) 0/ 48( 0%) 28/ 48( 58%) 1/16( 6%) 7/16( 43%) 0/16( 0%)
B: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: e:\juzhenjianpan\yima.rpt
yima
** EQUATIONS **
kin0 : INPUT;
kin1 : INPUT;
kin2 : INPUT;
kin3 : INPUT;
sel0 : INPUT;
sel1 : INPUT;
sel2 : INPUT;
-- Node name is 'Y0'
-- Equation name is 'Y0', type is output
Y0 = _LC5_A16;
-- Node name is 'Y1'
-- Equation name is 'Y1', type is output
Y1 = _LC2_A16;
-- Node name is 'Y2'
-- Equation name is 'Y2', type is output
Y2 = _LC2_A22;
-- Node name is 'Y3'
-- Equation name is 'Y3', type is output
Y3 = _LC1_A13;
-- Node name is 'Y4'
-- Equation name is 'Y4', type is output
Y4 = _LC7_A13;
-- Node name is 'Y5'
-- Equation name is 'Y5', type is output
Y5 = _LC1_A16;
-- Node name is 'Y6'
-- Equation name is 'Y6', type is output
Y6 = _LC8_A13;
-- Node name is '~96~1'
-- Equation name is '~96~1', location is LC2_A18, type is buried.
-- synthesized logic cell
_LC2_A18 = LCELL( _EQ001);
_EQ001 = !kin0 & kin1 & kin2 & kin3;
-- Node name is ':96'
-- Equation name is '_LC4_A16', type is buried
!_LC4_A16 = _LC4_A16~NOT;
_LC4_A16~NOT = LCELL( _EQ002);
_EQ002 = sel2
# sel1
# !_LC2_A18
# sel0;
-- Node name is '~106~1'
-- Equation name is '~106~1', location is LC4_A18, type is buried.
-- synthesized logic cell
_LC4_A18 = LCELL( _EQ003);
_EQ003 = kin0 & !kin1 & kin2 & kin3;
-- Node name is ':106'
-- Equation name is '_LC1_A18', type is buried
_LC1_A18 = LCELL( _EQ004);
_EQ004 = _LC4_A18 & !sel0 & !sel1 & !sel2;
-- Node name is ':116'
-- Equation name is '_LC4_A13', type is buried
!_LC4_A13 = _LC4_A13~NOT;
_LC4_A13~NOT = LCELL( _EQ005);
_EQ005 = sel2
# sel1
# !_LC2_A18
# !sel0;
-- Node name is ':126'
-- Equation name is '_LC3_A13', type is buried
!_LC3_A13 = _LC3_A13~NOT;
_LC3_A13~NOT = LCELL( _EQ006);
_EQ006 = !_LC4_A18
# sel1
# sel2
# !sel0;
-- Node name is '~136~1'
-- Equation name is '~136~1', location is LC1_A14, type is buried.
-- synthesized logic cell
_LC1_A14 = LCELL( _EQ007);
_EQ007 = _LC2_A18 & sel1 & !sel2;
-- Node name is ':136'
-- Equation name is '_LC4_A15', type is buried
!_LC4_A15 = _LC4_A15~NOT;
_LC4_A15~NOT = LCELL( _EQ008);
_EQ008 = !_LC1_A14
# sel0;
-- Node name is '~146~1'
-- Equation name is '~146~1', location is LC7_A15, type is buried.
-- synthesized logic cell
!_LC7_A15 = _LC7_A15~NOT;
_LC7_A15~NOT = LCELL( _EQ009);
_EQ009 = sel2
# !sel1
# !_LC7_A18;
-- Node name is ':146'
-- Equation name is '_LC1_A15', type is buried
_LC1_A15 = LCELL( _EQ010);
_EQ010 = _LC7_A15 & !sel0;
-- Node name is ':156'
-- Equation name is '_LC7_A22', type is buried
!_LC7_A22 = _LC7_A22~NOT;
_LC7_A22~NOT = LCELL( _EQ011);
_EQ011 = !_LC1_A14
# !sel0;
-- Node name is ':166'
-- Equation name is '_LC3_A15', type is buried
_LC3_A15 = LCELL( _EQ012);
_EQ012 = _LC7_A15 & sel0;
-- Node name is ':176'
-- Equation name is '_LC5_A18', type is buried
_LC5_A18 = LCELL( _EQ013);
_EQ013 = _LC4_A18 & !sel0 & !sel1 & sel2;
-- Node name is '~186~1'
-- Equation name is '~186~1', location is LC7_A18, type is buried.
-- synthesized logic cell
!_LC7_A18 = _LC7_A18~NOT;
_LC7_A18~NOT = LCELL( _EQ014);
_EQ014 = !kin3
# kin2
# !kin0
# !kin1;
-- Node name is ':186'
-- Equation name is '_LC2_A15', type is buried
_LC2_A15 = LCELL( _EQ015);
_EQ015 = _LC7_A18 & !sel0 & !sel1 & sel2;
-- Node name is ':196'
-- Equation name is '_LC3_A18', type is buried
_LC3_A18 = LCELL( _EQ016);
_EQ016 = _LC4_A18 & sel0 & !sel1 & sel2;
-- Node name is ':206'
-- Equation name is '_LC6_A15', type is buried
_LC6_A15 = LCELL( _EQ017);
_EQ017 = _LC7_A18 & sel0 & !sel1 & sel2;
-- Node name is ':216'
-- Equation name is '_LC2_A14', type is buried
_LC2_A14 = LCELL( _EQ018);
_EQ018 = _LC2_A18 & !sel0 & sel1 & sel2;
-- Node name is ':226'
-- Equation name is '_LC8_A18', type is buried
_LC8_A18 = LCELL( _EQ019);
_EQ019 = _LC4_A18 & !sel0 & sel1 & sel2;
-- Node name is ':236'
-- Equation name is '_LC4_A14', type is buried
_LC4_A14 = LCELL( _EQ020);
_EQ020 = _LC2_A18 & sel0 & sel1 & sel2;
-- Node name is ':246'
-- Equation name is '_LC6_A18', type is buried
_LC6_A18 = LCELL( _EQ021);
_EQ021 = _LC4_A18 & sel0 & sel1 & sel2;
-- Node name is ':282'
-- Equation name is '_LC5_A19', type is buried
_LC5_A19 = LCELL( _EQ022);
_EQ022 = !_LC2_A14 & _LC8_A18
# !_LC2_A14 & _LC4_A14;
-- Node name is '~328~1'
-- Equation name is '~328~1', location is LC3_A22, type is buried.
-- synthesized logic cell
_LC3_A22 = LCELL( _EQ023);
_EQ023 = _LC4_A22
# _LC4_A15
# _LC1_A15;
-- Node name is '~328~2'
-- Equation name is '~328~2', location is LC6_A13, type is buried.
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