yima.rpt

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-- synthesized logic cell 
_LC6_A13 = LCELL( _EQ024);
  _EQ024 =  _LC5_A19
         #  _LC3_A13
         #  _LC6_A19;

-- Node name is '~346~1' 
-- Equation name is '~346~1', location is LC3_A16, type is buried.
-- synthesized logic cell 
_LC3_A16 = LCELL( _EQ025);
  _EQ025 =  _LC4_A16
         #  _LC1_A18;

-- Node name is ':346' 
-- Equation name is '_LC8_A13', type is buried 
_LC8_A13 = LCELL( _EQ026);
  _EQ026 = !_LC4_A13 &  _LC6_A13
         #  _LC3_A22 & !_LC4_A13
         #  _LC3_A16;

-- Node name is ':361' 
-- Equation name is '_LC8_A19', type is buried 
!_LC8_A19 = _LC8_A19~NOT;
_LC8_A19~NOT = LCELL( _EQ027);
  _EQ027 = !_LC2_A14 & !_LC8_A18;

-- Node name is ':367' 
-- Equation name is '_LC7_A16', type is buried 
_LC7_A16 = LCELL( _EQ028);
  _EQ028 = !_LC6_A15 &  _LC8_A18
         #  _LC2_A14 & !_LC6_A15
         #  _LC3_A18;

-- Node name is ':387' 
-- Equation name is '_LC8_A16', type is buried 
_LC8_A16 = LCELL( _EQ029);
  _EQ029 = !_LC1_A15 & !_LC2_A15 &  _LC7_A16
         # !_LC1_A15 &  _LC4_A22;

-- Node name is '~391~1' 
-- Equation name is '~391~1', location is LC6_A16, type is buried.
-- synthesized logic cell 
!_LC6_A16 = _LC6_A16~NOT;
_LC6_A16~NOT = LCELL( _EQ030);
  _EQ030 =  _LC2_A13 & !_LC4_A15;

-- Node name is ':397' 
-- Equation name is '_LC1_A16', type is buried 
_LC1_A16 = LCELL( _EQ031);
  _EQ031 = !_LC1_A18 &  _LC8_A16
         # !_LC1_A18 &  _LC6_A16
         #  _LC4_A16;

-- Node name is ':412' 
-- Equation name is '_LC7_A19', type is buried 
_LC7_A19 = LCELL( _EQ032);
  _EQ032 =  _LC8_A18
         #  _LC2_A14
         #  _LC4_A14
         #  _LC6_A18;

-- Node name is ':426' 
-- Equation name is '_LC1_A19', type is buried 
_LC1_A19 = LCELL( _EQ033);
  _EQ033 = !_LC2_A15 & !_LC6_A15 &  _LC7_A19
         # !_LC2_A15 &  _LC3_A18;

-- Node name is ':441' 
-- Equation name is '_LC1_A22', type is buried 
_LC1_A22 = LCELL( _EQ034);
  _EQ034 = !_LC1_A15 &  _LC1_A19 & !_LC4_A15
         # !_LC1_A15 & !_LC4_A15 &  _LC4_A22;

-- Node name is ':448' 
-- Equation name is '_LC7_A13', type is buried 
_LC7_A13 = LCELL( _EQ035);
  _EQ035 =  _LC1_A22
         #  _LC3_A13
         #  _LC4_A13
         #  _LC3_A16;

-- Node name is ':471' 
-- Equation name is '_LC4_A19', type is buried 
_LC4_A19 = LCELL( _EQ036);
  _EQ036 =  _LC4_A14 & !_LC6_A15 & !_LC8_A19
         # !_LC6_A15 &  _LC6_A18 & !_LC8_A19;

-- Node name is '~487~1' 
-- Equation name is '~487~1', location is LC4_A22, type is buried.
-- synthesized logic cell 
_LC4_A22 = LCELL( _EQ037);
  _EQ037 =  _LC3_A15
         #  _LC5_A18
         #  _LC1_A14 &  sel0;

-- Node name is '~487~2' 
-- Equation name is '~487~2', location is LC5_A13, type is buried.
-- synthesized logic cell 
_LC5_A13 = LCELL( _EQ038);
  _EQ038 =  _LC3_A18
         #  _LC2_A15
         #  _LC4_A19;

-- Node name is ':499' 
-- Equation name is '_LC1_A13', type is buried 
_LC1_A13 = LCELL( _EQ039);
  _EQ039 =  _LC2_A13 &  _LC3_A22
         #  _LC2_A13 &  _LC5_A13
         #  _LC3_A16;

-- Node name is ':517' 
-- Equation name is '_LC3_A19', type is buried 
_LC3_A19 = LCELL( _EQ040);
  _EQ040 = !_LC2_A14 &  _LC8_A18
         # !_LC2_A14 &  _LC6_A18
         #  _LC6_A15;

-- Node name is '~529~1' 
-- Equation name is '~529~1', location is LC5_A22, type is buried.
-- synthesized logic cell 
_LC5_A22 = LCELL( _EQ041);
  _EQ041 =  _LC3_A15
         #  _LC5_A18;

-- Node name is ':529' 
-- Equation name is '_LC6_A22', type is buried 
_LC6_A22 = LCELL( _EQ042);
  _EQ042 = !_LC3_A18 &  _LC3_A19
         #  _LC5_A22
         #  _LC2_A15;

-- Node name is ':538' 
-- Equation name is '_LC8_A22', type is buried 
_LC8_A22 = LCELL( _EQ043);
  _EQ043 =  _LC4_A15
         #  _LC1_A15
         #  _LC6_A22 & !_LC7_A22;

-- Node name is ':550' 
-- Equation name is '_LC2_A22', type is buried 
_LC2_A22 = LCELL( _EQ044);
  _EQ044 =  _LC2_A13 &  _LC8_A22
         #  _LC3_A16;

-- Node name is ':588' 
-- Equation name is '_LC5_A15', type is buried 
_LC5_A15 = LCELL( _EQ045);
  _EQ045 = !_LC1_A14 &  _LC3_A15
         #  _LC3_A15 & !sel0
         # !_LC1_A14 &  _LC2_A19
         #  _LC2_A19 & !sel0;

-- Node name is ':601' 
-- Equation name is '_LC2_A16', type is buried 
_LC2_A16 = LCELL( _EQ046);
  _EQ046 =  _LC3_A16
         #  _LC1_A15 & !_LC6_A16
         #  _LC5_A15 & !_LC6_A16;

-- Node name is '~628~1' 
-- Equation name is '~628~1', location is LC6_A19, type is buried.
-- synthesized logic cell 
_LC6_A19 = LCELL( _EQ047);
  _EQ047 =  _LC6_A15
         #  _LC3_A18
         #  _LC2_A15;

-- Node name is ':628' 
-- Equation name is '_LC2_A19', type is buried 
_LC2_A19 = LCELL( _EQ048);
  _EQ048 =  _LC7_A19
         #  _LC6_A19
         #  _LC5_A18;

-- Node name is ':640' 
-- Equation name is '_LC8_A15', type is buried 
_LC8_A15 = LCELL( _EQ049);
  _EQ049 =  _LC1_A14
         #  _LC2_A19 & !_LC7_A15;

-- Node name is '~651~1' 
-- Equation name is '~651~1', location is LC2_A13, type is buried.
-- synthesized logic cell 
_LC2_A13 = LCELL( _EQ050);
  _EQ050 = !_LC3_A13 & !_LC4_A13;

-- Node name is ':654' 
-- Equation name is '_LC5_A16', type is buried 
_LC5_A16 = LCELL( _EQ051);
  _EQ051 =  _LC1_A18 & !_LC4_A16
         #  _LC2_A13 & !_LC4_A16 &  _LC8_A15;



Project Information                                  e:\juzhenjianpan\yima.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'ACEX1K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:01


Memory Allocated
-----------------

Peak memory allocated during compilation  = 16,203K