full_adder.fnsim.qmsg

这是一个基于嵌入式的利用硬件高级描述语言编写的全加器程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 7.2 Build 151 09/26/2007 SJ Full Version " "Info: Version 7.2 Build 151 09/26/2007 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0} { "Info" "IQEXE_START_BANNER_TIME" "Tue Nov 04 01:51:08 2008 " "Info: Processing started: Tue Nov 04 01:51:08 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off full_adder -c full_adder --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off full_adder -c full_adder --generate_functional_sim_netlist" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0}
{ "Warning" "WSGN_FILE_IS_MISSING" "C:/altera/jobs/full_adder.vhd " "Warning: Can't analyze file -- file C:/altera/jobs/full_adder.vhd is missing" {  } {  } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "half_adder.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file half_adder.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 half_adder-half_adder " "Info: Found design unit 1: half_adder-half_adder" {  } { { "half_adder.vhd" "" { Text "C:/altera/jobs/half_adder.vhd" 11 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 half_adder " "Info: Found entity 1: half_adder" {  } { { "half_adder.vhd" "" { Text "C:/altera/jobs/half_adder.vhd" 3 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "full_adder.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file full_adder.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 full_adder " "Info: Found entity 1: full_adder" {  } { { "full_adder.bdf" "" { Schematic "C:/altera/jobs/full_adder.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "full_adder " "Info: Elaborating entity \"full_adder\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "half_adder half_adder:inst " "Info: Elaborating entity \"half_adder\" for hierarchy \"half_adder:inst\"" {  } { { "full_adder.bdf" "inst" { Schematic "C:/altera/jobs/full_adder.bdf" { { 64 336 432 160 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 1  Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "154 " "Info: Allocated 154 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Tue Nov 04 01:51:19 2008 " "Info: Processing ended: Tue Nov 04 01:51:19 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:11 " "Info: Elapsed time: 00:00:11" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}