half_adder.vhd

来自「这是一个基于嵌入式的利用硬件高级描述语言编写的全加器程序」· VHDL 代码 · 共 19 行

library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity half_adder is
	    port(
		   a : in STD_LOGIC;
		   b : in STD_LOGIC;
		   s : out STD_LOGIC;
		   co : out STD_LOGIC
	       );
end half_adder;
architecture half_adder of half_adder is
signal c,d:std_logic;
begin
       c<=a or b;
       d<=a nand b;
       co<=not d;
       s<=c and d;
end half_adder;