mux_frc.tdf

用VHDL语言设计简单的CPU

--lpm_mux CASCADE_CHAIN="IGNORE" DEVICE_FAMILY="Stratix II" IGNORE_CASCADE_BUFFERS="OFF" LPM_SIZE=256 LPM_WIDTH=1 LPM_WIDTHS=8 data result sel
--VERSION_BEGIN 7.2SP3 cbx_lpm_mux 2007:05:11:14:07:38:SJ cbx_mgl 2007:08:03:15:48:12:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 85 
SUBDESIGN mux_frc
( 
	data[255..0]	:	input;
	result[0..0]	:	output;
	sel[7..0]	:	input;
) 
VARIABLE
	l1_w0_n0_mux_dataout	:	WIRE;
	l1_w0_n100_mux_dataout	:	WIRE;
	l1_w0_n101_mux_dataout	:	WIRE;
	l1_w0_n102_mux_dataout	:	WIRE;
	l1_w0_n103_mux_dataout	:	WIRE;
	l1_w0_n104_mux_dataout	:	WIRE;
	l1_w0_n105_mux_dataout	:	WIRE;
	l1_w0_n106_mux_dataout	:	WIRE;
	l1_w0_n107_mux_dataout	:	WIRE;
	l1_w0_n108_mux_dataout	:	WIRE;
	l1_w0_n109_mux_dataout	:	WIRE;
	l1_w0_n10_mux_dataout	:	WIRE;
	l1_w0_n110_mux_dataout	:	WIRE;
	l1_w0_n111_mux_dataout	:	WIRE;
	l1_w0_n112_mux_dataout	:	WIRE;
	l1_w0_n113_mux_dataout	:	WIRE;
	l1_w0_n114_mux_dataout	:	WIRE;
	l1_w0_n115_mux_dataout	:	WIRE;
	l1_w0_n116_mux_dataout	:	WIRE;
	l1_w0_n117_mux_dataout	:	WIRE;
	l1_w0_n118_mux_dataout	:	WIRE;
	l1_w0_n119_mux_dataout	:	WIRE;
	l1_w0_n11_mux_dataout	:	WIRE;
	l1_w0_n120_mux_dataout	:	WIRE;
	l1_w0_n121_mux_dataout	:	WIRE;
	l1_w0_n122_mux_dataout	:	WIRE;
	l1_w0_n123_mux_dataout	:	WIRE;
	l1_w0_n124_mux_dataout	:	WIRE;
	l1_w0_n125_mux_dataout	:	WIRE;
	l1_w0_n126_mux_dataout	:	WIRE;
	l1_w0_n127_mux_dataout	:	WIRE;
	l1_w0_n12_mux_dataout	:	WIRE;
	l1_w0_n13_mux_dataout	:	WIRE;
	l1_w0_n14_mux_dataout	:	WIRE;
	l1_w0_n15_mux_dataout	:	WIRE;
	l1_w0_n16_mux_dataout	:	WIRE;
	l1_w0_n17_mux_dataout	:	WIRE;
	l1_w0_n18_mux_dataout	:	WIRE;
	l1_w0_n19_mux_dataout	:	WIRE;
	l1_w0_n1_mux_dataout	:	WIRE;
	l1_w0_n20_mux_dataout	:	WIRE;
	l1_w0_n21_mux_dataout	:	WIRE;
	l1_w0_n22_mux_dataout	:	WIRE;
	l1_w0_n23_mux_dataout	:	WIRE;
	l1_w0_n24_mux_dataout	:	WIRE;
	l1_w0_n25_mux_dataout	:	WIRE;
	l1_w0_n26_mux_dataout	:	WIRE;
	l1_w0_n27_mux_dataout	:	WIRE;
	l1_w0_n28_mux_dataout	:	WIRE;
	l1_w0_n29_mux_dataout	:	WIRE;
	l1_w0_n2_mux_dataout	:	WIRE;
	l1_w0_n30_mux_dataout	:	WIRE;
	l1_w0_n31_mux_dataout	:	WIRE;
	l1_w0_n32_mux_dataout	:	WIRE;
	l1_w0_n33_mux_dataout	:	WIRE;
	l1_w0_n34_mux_dataout	:	WIRE;
	l1_w0_n35_mux_dataout	:	WIRE;
	l1_w0_n36_mux_dataout	:	WIRE;
	l1_w0_n37_mux_dataout	:	WIRE;
	l1_w0_n38_mux_dataout	:	WIRE;
	l1_w0_n39_mux_dataout	:	WIRE;
	l1_w0_n3_mux_dataout	:	WIRE;
	l1_w0_n40_mux_dataout	:	WIRE;
	l1_w0_n41_mux_dataout	:	WIRE;
	l1_w0_n42_mux_dataout	:	WIRE;
	l1_w0_n43_mux_dataout	:	WIRE;
	l1_w0_n44_mux_dataout	:	WIRE;
	l1_w0_n45_mux_dataout	:	WIRE;
	l1_w0_n46_mux_dataout	:	WIRE;
	l1_w0_n47_mux_dataout	:	WIRE;
	l1_w0_n48_mux_dataout	:	WIRE;
	l1_w0_n49_mux_dataout	:	WIRE;
	l1_w0_n4_mux_dataout	:	WIRE;
	l1_w0_n50_mux_dataout	:	WIRE;
	l1_w0_n51_mux_dataout	:	WIRE;
	l1_w0_n52_mux_dataout	:	WIRE;
	l1_w0_n53_mux_dataout	:	WIRE;
	l1_w0_n54_mux_dataout	:	WIRE;
	l1_w0_n55_mux_dataout	:	WIRE;
	l1_w0_n56_mux_dataout	:	WIRE;
	l1_w0_n57_mux_dataout	:	WIRE;
	l1_w0_n58_mux_dataout	:	WIRE;
	l1_w0_n59_mux_dataout	:	WIRE;
	l1_w0_n5_mux_dataout	:	WIRE;
	l1_w0_n60_mux_dataout	:	WIRE;
	l1_w0_n61_mux_dataout	:	WIRE;
	l1_w0_n62_mux_dataout	:	WIRE;
	l1_w0_n63_mux_dataout	:	WIRE;
	l1_w0_n64_mux_dataout	:	WIRE;
	l1_w0_n65_mux_dataout	:	WIRE;
	l1_w0_n66_mux_dataout	:	WIRE;
	l1_w0_n67_mux_dataout	:	WIRE;
	l1_w0_n68_mux_dataout	:	WIRE;
	l1_w0_n69_mux_dataout	:	WIRE;
	l1_w0_n6_mux_dataout	:	WIRE;
	l1_w0_n70_mux_dataout	:	WIRE;
	l1_w0_n71_mux_dataout	:	WIRE;
	l1_w0_n72_mux_dataout	:	WIRE;
	l1_w0_n73_mux_dataout	:	WIRE;
	l1_w0_n74_mux_dataout	:	WIRE;
	l1_w0_n75_mux_dataout	:	WIRE;
	l1_w0_n76_mux_dataout	:	WIRE;
	l1_w0_n77_mux_dataout	:	WIRE;
	l1_w0_n78_mux_dataout	:	WIRE;
	l1_w0_n79_mux_dataout	:	WIRE;
	l1_w0_n7_mux_dataout	:	WIRE;
	l1_w0_n80_mux_dataout	:	WIRE;
	l1_w0_n81_mux_dataout	:	WIRE;
	l1_w0_n82_mux_dataout	:	WIRE;
	l1_w0_n83_mux_dataout	:	WIRE;
	l1_w0_n84_mux_dataout	:	WIRE;
	l1_w0_n85_mux_dataout	:	WIRE;
	l1_w0_n86_mux_dataout	:	WIRE;
	l1_w0_n87_mux_dataout	:	WIRE;
	l1_w0_n88_mux_dataout	:	WIRE;
	l1_w0_n89_mux_dataout	:	WIRE;
	l1_w0_n8_mux_dataout	:	WIRE;
	l1_w0_n90_mux_dataout	:	WIRE;
	l1_w0_n91_mux_dataout	:	WIRE;
	l1_w0_n92_mux_dataout	:	WIRE;
	l1_w0_n93_mux_dataout	:	WIRE;
	l1_w0_n94_mux_dataout	:	WIRE;
	l1_w0_n95_mux_dataout	:	WIRE;
	l1_w0_n96_mux_dataout	:	WIRE;
	l1_w0_n97_mux_dataout	:	WIRE;
	l1_w0_n98_mux_dataout	:	WIRE;
	l1_w0_n99_mux_dataout	:	WIRE;
	l1_w0_n9_mux_dataout	:	WIRE;
	l2_w0_n0_mux_dataout	:	WIRE;
	l2_w0_n10_mux_dataout	:	WIRE;
	l2_w0_n11_mux_dataout	:	WIRE;
	l2_w0_n12_mux_dataout	:	WIRE;
	l2_w0_n13_mux_dataout	:	WIRE;
	l2_w0_n14_mux_dataout	:	WIRE;
	l2_w0_n15_mux_dataout	:	WIRE;
	l2_w0_n16_mux_dataout	:	WIRE;
	l2_w0_n17_mux_dataout	:	WIRE;
	l2_w0_n18_mux_dataout	:	WIRE;
	l2_w0_n19_mux_dataout	:	WIRE;
	l2_w0_n1_mux_dataout	:	WIRE;
	l2_w0_n20_mux_dataout	:	WIRE;
	l2_w0_n21_mux_dataout	:	WIRE;
	l2_w0_n22_mux_dataout	:	WIRE;
	l2_w0_n23_mux_dataout	:	WIRE;
	l2_w0_n24_mux_dataout	:	WIRE;
	l2_w0_n25_mux_dataout	:	WIRE;
	l2_w0_n26_mux_dataout	:	WIRE;
	l2_w0_n27_mux_dataout	:	WIRE;
	l2_w0_n28_mux_dataout	:	WIRE;
	l2_w0_n29_mux_dataout	:	WIRE;
	l2_w0_n2_mux_dataout	:	WIRE;
	l2_w0_n30_mux_dataout	:	WIRE;
	l2_w0_n31_mux_dataout	:	WIRE;
	l2_w0_n32_mux_dataout	:	WIRE;
	l2_w0_n33_mux_dataout	:	WIRE;