cpu.fnsim.qmsg

用VHDL语言设计简单的CPU

{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mbr mbr:inst3 " "Info: Elaborating entity \"mbr\" for hierarchy \"mbr:inst3\"" {  } { { "cpu.bdf" "inst3" { Schematic "F:/another way/cpu/cpu.bdf" { { 208 24 240 336 "inst3" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Warning" "WSGN_SEARCH_FILE" "lpm_ram_dq0.vhd 2 1 " "Warning: Using design file lpm_ram_dq0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 lpm_ram_dq0-SYN " "Info: Found design unit 1: lpm_ram_dq0-SYN" {  } { { "lpm_ram_dq0.vhd" "" { Text "F:/another way/cpu/lpm_ram_dq0.vhd" 54 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0 "" 0} { "Info" "ISGN_ENTITY_NAME" "1 lpm_ram_dq0 " "Info: Found entity 1: lpm_ram_dq0" {  } { { "lpm_ram_dq0.vhd" "" { Text "F:/another way/cpu/lpm_ram_dq0.vhd" 42 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!llu! design units and %3!llu! entities in project" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "lpm_ram_dq0 lpm_ram_dq0:inst7 " "Info: Elaborating entity \"lpm_ram_dq0\" for hierarchy \"lpm_ram_dq0:inst7\"" {  } { { "cpu.bdf" "inst7" { Schematic "F:/another way/cpu/cpu.bdf" { { 464 24 184 576 "inst7" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram lpm_ram_dq0:inst7\|altsyncram:altsyncram_component " "Info: Elaborating entity \"altsyncram\" for hierarchy \"lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\"" {  } { { "lpm_ram_dq0.vhd" "altsyncram_component" { Text "F:/another way/cpu/lpm_ram_dq0.vhd" 89 0 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "lpm_ram_dq0:inst7\|altsyncram:altsyncram_component " "Info: Elaborated megafunction instantiation \"lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\"" {  } { { "lpm_ram_dq0.vhd" "" { Text "F:/another way/cpu/lpm_ram_dq0.vhd" 89 0 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_3ac1.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3ac1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_3ac1 " "Info: Found entity 1: altsyncram_3ac1" {  } { { "db/altsyncram_3ac1.tdf" "" { Text "F:/another way/cpu/db/altsyncram_3ac1.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_3ac1 lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated " "Info: Elaborating entity \"altsyncram_3ac1\" for hierarchy \"lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/altsyncram.tdf" 918 4 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "mar mar:inst6 " "Info: Elaborating entity \"mar\" for hierarchy \"mar:inst6\"" {  } { { "cpu.bdf" "inst6" { Schematic "F:/another way/cpu/cpu.bdf" { { 96 416 584 224 "inst6" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pc pc:inst5 " "Info: Elaborating entity \"pc\" for hierarchy \"pc:inst5\"" {  } { { "cpu.bdf" "inst5" { Schematic "F:/another way/cpu/cpu.bdf" { { -16 416 592 80 "inst5" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0}
{ "Info" "ILPMS_INFERENCING_SUMMARY" "8 " "Info: Inferred 8 megafunctions from design logic" { { "Info" "ILPMS_LPM_MUX_INFERRED" "control_unit:inst2\|Mux0 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"control_unit:inst2\|Mux0\"" {  } { { "control_unit.vhd" "Mux0" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "control_unit:inst2\|Mux1 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"control_unit:inst2\|Mux1\"" {  } { { "control_unit.vhd" "Mux1" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "control_unit:inst2\|Mux2 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"control_unit:inst2\|Mux2\"" {  } { { "control_unit.vhd" "Mux2" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "control_unit:inst2\|Mux3 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"control_unit:inst2\|Mux3\"" {  } { { "control_unit.vhd" "Mux3" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "control_unit:inst2\|Mux4 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"control_unit:inst2\|Mux4\"" {  } { { "control_unit.vhd" "Mux4" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "control_unit:inst2\|Mux5 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"control_unit:inst2\|Mux5\"" {  } { { "control_unit.vhd" "Mux5" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "control_unit:inst2\|Mux6 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"control_unit:inst2\|Mux6\"" {  } { { "control_unit.vhd" "Mux6" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0} { "Info" "ILPMS_LPM_MUX_INFERRED" "control_unit:inst2\|Mux7 lpm_mux " "Info: Inferred mux megafunction (\"lpm_mux\") from the following logic: \"control_unit:inst2\|Mux7\"" {  } { { "control_unit.vhd" "Mux7" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Inferred mux megafunction (\"%2!s!\") from the following logic: \"%1!s!\"" 0 0 "" 0}  } {  } 0 0 "Inferred %1!llu! megafunctions from design logic" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/lpm_mux.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/lpm_mux.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_mux " "Info: Found entity 1: lpm_mux" {  } { { "lpm_mux.tdf" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/lpm_mux.tdf" 74 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "control_unit:inst2\|lpm_mux:Mux0 " "Info: Elaborated megafunction instantiation \"control_unit:inst2\|lpm_mux:Mux0\"" {  } { { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/mux_frc.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file db/mux_frc.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 mux_frc " "Info: Found entity 1: mux_frc" {  } { { "db/mux_frc.tdf" "" { Text "F:/another way/cpu/db/mux_frc.tdf" 22 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "control_unit:inst2\|lpm_mux:Mux1 " "Info: Elaborated megafunction instantiation \"control_unit:inst2\|lpm_mux:Mux1\"" {  } { { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "control_unit:inst2\|lpm_mux:Mux2 " "Info: Elaborated megafunction instantiation \"control_unit:inst2\|lpm_mux:Mux2\"" {  } { { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "control_unit:inst2\|lpm_mux:Mux3 " "Info: Elaborated megafunction instantiation \"control_unit:inst2\|lpm_mux:Mux3\"" {  } { { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "control_unit:inst2\|lpm_mux:Mux4 " "Info: Elaborated megafunction instantiation \"control_unit:inst2\|lpm_mux:Mux4\"" {  } { { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "control_unit:inst2\|lpm_mux:Mux5 " "Info: Elaborated megafunction instantiation \"control_unit:inst2\|lpm_mux:Mux5\"" {  } { { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "control_unit:inst2\|lpm_mux:Mux6 " "Info: Elaborated megafunction instantiation \"control_unit:inst2\|lpm_mux:Mux6\"" {  } { { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "ISGN_ELABORATION_HEADER" "control_unit:inst2\|lpm_mux:Mux7 " "Info: Elaborated megafunction instantiation \"control_unit:inst2\|lpm_mux:Mux7\"" {  } { { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 2 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "170 " "Info: Allocated 170 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 29 16:06:42 2009 " "Info: Processing ended: Sun Mar 29 16:06:42 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:06 " "Info: Elapsed time: 00:00:06" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}