cpu.hier_info

用VHDL语言设计简单的CPU

eccstatus[2] <= <GND>


|cpu|lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[2] => ram_block1a0.PORTAADDR2
address_a[2] => ram_block1a1.PORTAADDR2
address_a[2] => ram_block1a2.PORTAADDR2
address_a[2] => ram_block1a3.PORTAADDR2
address_a[2] => ram_block1a4.PORTAADDR2
address_a[2] => ram_block1a5.PORTAADDR2
address_a[2] => ram_block1a6.PORTAADDR2
address_a[2] => ram_block1a7.PORTAADDR2
address_a[2] => ram_block1a8.PORTAADDR2
address_a[2] => ram_block1a9.PORTAADDR2
address_a[2] => ram_block1a10.PORTAADDR2
address_a[2] => ram_block1a11.PORTAADDR2
address_a[2] => ram_block1a12.PORTAADDR2
address_a[2] => ram_block1a13.PORTAADDR2
address_a[2] => ram_block1a14.PORTAADDR2
address_a[2] => ram_block1a15.PORTAADDR2
address_a[3] => ram_block1a0.PORTAADDR3
address_a[3] => ram_block1a1.PORTAADDR3
address_a[3] => ram_block1a2.PORTAADDR3
address_a[3] => ram_block1a3.PORTAADDR3
address_a[3] => ram_block1a4.PORTAADDR3
address_a[3] => ram_block1a5.PORTAADDR3
address_a[3] => ram_block1a6.PORTAADDR3
address_a[3] => ram_block1a7.PORTAADDR3
address_a[3] => ram_block1a8.PORTAADDR3
address_a[3] => ram_block1a9.PORTAADDR3
address_a[3] => ram_block1a10.PORTAADDR3
address_a[3] => ram_block1a11.PORTAADDR3
address_a[3] => ram_block1a12.PORTAADDR3
address_a[3] => ram_block1a13.PORTAADDR3
address_a[3] => ram_block1a14.PORTAADDR3
address_a[3] => ram_block1a15.PORTAADDR3
address_a[4] => ram_block1a0.PORTAADDR4
address_a[4] => ram_block1a1.PORTAADDR4
address_a[4] => ram_block1a2.PORTAADDR4
address_a[4] => ram_block1a3.PORTAADDR4
address_a[4] => ram_block1a4.PORTAADDR4
address_a[4] => ram_block1a5.PORTAADDR4
address_a[4] => ram_block1a6.PORTAADDR4
address_a[4] => ram_block1a7.PORTAADDR4
address_a[4] => ram_block1a8.PORTAADDR4
address_a[4] => ram_block1a9.PORTAADDR4
address_a[4] => ram_block1a10.PORTAADDR4
address_a[4] => ram_block1a11.PORTAADDR4
address_a[4] => ram_block1a12.PORTAADDR4
address_a[4] => ram_block1a13.PORTAADDR4
address_a[4] => ram_block1a14.PORTAADDR4
address_a[4] => ram_block1a15.PORTAADDR4
address_a[5] => ram_block1a0.PORTAADDR5
address_a[5] => ram_block1a1.PORTAADDR5
address_a[5] => ram_block1a2.PORTAADDR5
address_a[5] => ram_block1a3.PORTAADDR5
address_a[5] => ram_block1a4.PORTAADDR5
address_a[5] => ram_block1a5.PORTAADDR5
address_a[5] => ram_block1a6.PORTAADDR5
address_a[5] => ram_block1a7.PORTAADDR5
address_a[5] => ram_block1a8.PORTAADDR5
address_a[5] => ram_block1a9.PORTAADDR5
address_a[5] => ram_block1a10.PORTAADDR5
address_a[5] => ram_block1a11.PORTAADDR5
address_a[5] => ram_block1a12.PORTAADDR5
address_a[5] => ram_block1a13.PORTAADDR5
address_a[5] => ram_block1a14.PORTAADDR5
address_a[5] => ram_block1a15.PORTAADDR5
address_a[6] => ram_block1a0.PORTAADDR6
address_a[6] => ram_block1a1.PORTAADDR6
address_a[6] => ram_block1a2.PORTAADDR6
address_a[6] => ram_block1a3.PORTAADDR6
address_a[6] => ram_block1a4.PORTAADDR6
address_a[6] => ram_block1a5.PORTAADDR6
address_a[6] => ram_block1a6.PORTAADDR6
address_a[6] => ram_block1a7.PORTAADDR6
address_a[6] => ram_block1a8.PORTAADDR6
address_a[6] => ram_block1a9.PORTAADDR6
address_a[6] => ram_block1a10.PORTAADDR6
address_a[6] => ram_block1a11.PORTAADDR6
address_a[6] => ram_block1a12.PORTAADDR6
address_a[6] => ram_block1a13.PORTAADDR6
address_a[6] => ram_block1a14.PORTAADDR6
address_a[6] => ram_block1a15.PORTAADDR6
address_a[7] => ram_block1a0.PORTAADDR7
address_a[7] => ram_block1a1.PORTAADDR7
address_a[7] => ram_block1a2.PORTAADDR7
address_a[7] => ram_block1a3.PORTAADDR7
address_a[7] => ram_block1a4.PORTAADDR7
address_a[7] => ram_block1a5.PORTAADDR7
address_a[7] => ram_block1a6.PORTAADDR7
address_a[7] => ram_block1a7.PORTAADDR7
address_a[7] => ram_block1a8.PORTAADDR7
address_a[7] => ram_block1a9.PORTAADDR7
address_a[7] => ram_block1a10.PORTAADDR7
address_a[7] => ram_block1a11.PORTAADDR7
address_a[7] => ram_block1a12.PORTAADDR7
address_a[7] => ram_block1a13.PORTAADDR7
address_a[7] => ram_block1a14.PORTAADDR7
address_a[7] => ram_block1a15.PORTAADDR7
clock0 => ram_block1a0.CLK0
clock0 => ram_block1a1.CLK0
clock0 => ram_block1a2.CLK0
clock0 => ram_block1a3.CLK0
clock0 => ram_block1a4.CLK0
clock0 => ram_block1a5.CLK0
clock0 => ram_block1a6.CLK0
clock0 => ram_block1a7.CLK0
clock0 => ram_block1a8.CLK0
clock0 => ram_block1a9.CLK0
clock0 => ram_block1a10.CLK0
clock0 => ram_block1a11.CLK0
clock0 => ram_block1a12.CLK0
clock0 => ram_block1a13.CLK0
clock0 => ram_block1a14.CLK0
clock0 => ram_block1a15.CLK0
data_a[0] => ram_block1a0.PORTADATAIN
data_a[1] => ram_block1a1.PORTADATAIN
data_a[2] => ram_block1a2.PORTADATAIN
data_a[3] => ram_block1a3.PORTADATAIN
data_a[4] => ram_block1a4.PORTADATAIN
data_a[5] => ram_block1a5.PORTADATAIN
data_a[6] => ram_block1a6.PORTADATAIN
data_a[7] => ram_block1a7.PORTADATAIN
data_a[8] => ram_block1a8.PORTADATAIN
data_a[9] => ram_block1a9.PORTADATAIN
data_a[10] => ram_block1a10.PORTADATAIN
data_a[11] => ram_block1a11.PORTADATAIN
data_a[12] => ram_block1a12.PORTADATAIN
data_a[13] => ram_block1a13.PORTADATAIN
data_a[14] => ram_block1a14.PORTADATAIN
data_a[15] => ram_block1a15.PORTADATAIN
q_a[0] <= ram_block1a0.PORTADATAOUT
q_a[1] <= ram_block1a1.PORTADATAOUT
q_a[2] <= ram_block1a2.PORTADATAOUT
q_a[3] <= ram_block1a3.PORTADATAOUT
q_a[4] <= ram_block1a4.PORTADATAOUT
q_a[5] <= ram_block1a5.PORTADATAOUT
q_a[6] <= ram_block1a6.PORTADATAOUT
q_a[7] <= ram_block1a7.PORTADATAOUT
q_a[8] <= ram_block1a8.PORTADATAOUT
q_a[9] <= ram_block1a9.PORTADATAOUT
q_a[10] <= ram_block1a10.PORTADATAOUT
q_a[11] <= ram_block1a11.PORTADATAOUT
q_a[12] <= ram_block1a12.PORTADATAOUT
q_a[13] <= ram_block1a13.PORTADATAOUT
q_a[14] <= ram_block1a14.PORTADATAOUT
q_a[15] <= ram_block1a15.PORTADATAOUT
wren_a => ram_block1a0.PORTAWE
wren_a => ram_block1a1.PORTAWE
wren_a => ram_block1a2.PORTAWE
wren_a => ram_block1a3.PORTAWE
wren_a => ram_block1a4.PORTAWE
wren_a => ram_block1a5.PORTAWE
wren_a => ram_block1a6.PORTAWE
wren_a => ram_block1a7.PORTAWE
wren_a => ram_block1a8.PORTAWE
wren_a => ram_block1a9.PORTAWE
wren_a => ram_block1a10.PORTAWE
wren_a => ram_block1a11.PORTAWE
wren_a => ram_block1a12.PORTAWE
wren_a => ram_block1a13.PORTAWE
wren_a => ram_block1a14.PORTAWE
wren_a => ram_block1a15.PORTAWE


|cpu|mar:inst6
pc[0] => mar_out~15.DATAB
pc[1] => mar_out~14.DATAB
pc[2] => mar_out~13.DATAB
pc[3] => mar_out~12.DATAB
pc[4] => mar_out~11.DATAB
pc[5] => mar_out~10.DATAB
pc[6] => mar_out~9.DATAB
pc[7] => mar_out~8.DATAB
mbr[0] => mar_out~7.DATAB
mbr[1] => mar_out~6.DATAB
mbr[2] => mar_out~5.DATAB
mbr[3] => mar_out~4.DATAB
mbr[4] => mar_out~3.DATAB
mbr[5] => mar_out~2.DATAB
mbr[6] => mar_out~1.DATAB
mbr[7] => mar_out~0.DATAB
cs[0] => ~NO_FANOUT~
cs[1] => ~NO_FANOUT~
cs[2] => ~NO_FANOUT~
cs[3] => ~NO_FANOUT~
cs[4] => ~NO_FANOUT~
cs[5] => ~NO_FANOUT~
cs[6] => ~NO_FANOUT~
cs[7] => ~NO_FANOUT~
cs[8] => ~NO_FANOUT~
cs[9] => ~NO_FANOUT~
cs[10] => ~NO_FANOUT~
cs[11] => ~NO_FANOUT~
cs[12] => mar_out~15.OUTPUTSELECT
cs[12] => mar_out~14.OUTPUTSELECT
cs[12] => mar_out~13.OUTPUTSELECT
cs[12] => mar_out~12.OUTPUTSELECT
cs[12] => mar_out~11.OUTPUTSELECT
cs[12] => mar_out~10.OUTPUTSELECT
cs[12] => mar_out~9.OUTPUTSELECT
cs[12] => mar_out~8.OUTPUTSELECT
cs[13] => mar_out~7.OUTPUTSELECT
cs[13] => mar_out~6.OUTPUTSELECT
cs[13] => mar_out~5.OUTPUTSELECT
cs[13] => mar_out~4.OUTPUTSELECT
cs[13] => mar_out~3.OUTPUTSELECT
cs[13] => mar_out~2.OUTPUTSELECT
cs[13] => mar_out~1.OUTPUTSELECT
cs[13] => mar_out~0.OUTPUTSELECT
cs[14] => ~NO_FANOUT~
cs[15] => ~NO_FANOUT~
cs[16] => ~NO_FANOUT~
cs[17] => ~NO_FANOUT~
cs[18] => ~NO_FANOUT~
cs[19] => ~NO_FANOUT~
cs[20] => ~NO_FANOUT~
cs[21] => ~NO_FANOUT~
cs[22] => ~NO_FANOUT~
cs[23] => ~NO_FANOUT~
cs[24] => ~NO_FANOUT~
cs[25] => ~NO_FANOUT~
cs[26] => ~NO_FANOUT~
cs[27] => ~NO_FANOUT~
cs[28] => ~NO_FANOUT~
cs[29] => ~NO_FANOUT~
cs[30] => ~NO_FANOUT~
cs[31] => ~NO_FANOUT~
clk => mar_out[7]~reg0.CLK
clk => mar_out[6]~reg0.CLK
clk => mar_out[5]~reg0.CLK
clk => mar_out[4]~reg0.CLK
clk => mar_out[3]~reg0.CLK
clk => mar_out[2]~reg0.CLK
clk => mar_out[1]~reg0.CLK
clk => mar_out[0]~reg0.CLK
mar_out[0] <= mar_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mar_out[1] <= mar_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mar_out[2] <= mar_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mar_out[3] <= mar_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mar_out[4] <= mar_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mar_out[5] <= mar_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mar_out[6] <= mar_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mar_out[7] <= mar_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|pc:inst5
mbr_in[0] => temp~15.DATAB
mbr_in[1] => temp~14.DATAB
mbr_in[2] => temp~13.DATAB
mbr_in[3] => temp~12.DATAB
mbr_in[4] => temp~11.DATAB
mbr_in[5] => temp~10.DATAB
mbr_in[6] => temp~9.DATAB
mbr_in[7] => temp~8.DATAB
cs[0] => ~NO_FANOUT~
cs[1] => ~NO_FANOUT~
cs[2] => ~NO_FANOUT~
cs[3] => ~NO_FANOUT~
cs[4] => ~NO_FANOUT~
cs[5] => ~NO_FANOUT~
cs[6] => ~NO_FANOUT~
cs[7] => ~NO_FANOUT~
cs[8] => ~NO_FANOUT~
cs[9] => ~NO_FANOUT~
cs[10] => ~NO_FANOUT~
cs[11] => ~NO_FANOUT~
cs[12] => ~NO_FANOUT~
cs[13] => ~NO_FANOUT~
cs[14] => ~NO_FANOUT~
cs[15] => ~NO_FANOUT~
cs[16] => ~NO_FANOUT~
cs[17] => ~NO_FANOUT~
cs[18] => temp~15.OUTPUTSELECT
cs[18] => temp~14.OUTPUTSELECT
cs[18] => temp~13.OUTPUTSELECT
cs[18] => temp~12.OUTPUTSELECT
cs[18] => temp~11.OUTPUTSELECT
cs[18] => temp~10.OUTPUTSELECT
cs[18] => temp~9.OUTPUTSELECT
cs[18] => temp~8.OUTPUTSELECT
cs[19] => temp~7.OUTPUTSELECT
cs[19] => temp~6.OUTPUTSELECT
cs[19] => temp~5.OUTPUTSELECT
cs[19] => temp~4.OUTPUTSELECT
cs[19] => temp~3.OUTPUTSELECT
cs[19] => temp~2.OUTPUTSELECT
cs[19] => temp~1.OUTPUTSELECT
cs[19] => temp~0.OUTPUTSELECT
cs[20] => temp~23.OUTPUTSELECT
cs[20] => temp~22.OUTPUTSELECT
cs[20] => temp~21.OUTPUTSELECT
cs[20] => temp~20.OUTPUTSELECT
cs[20] => temp~19.OUTPUTSELECT
cs[20] => temp~18.OUTPUTSELECT
cs[20] => temp~17.OUTPUTSELECT
cs[20] => temp~16.OUTPUTSELECT
cs[21] => ~NO_FANOUT~
cs[22] => ~NO_FANOUT~
cs[23] => ~NO_FANOUT~
cs[24] => ~NO_FANOUT~
cs[25] => ~NO_FANOUT~
cs[26] => ~NO_FANOUT~
cs[27] => ~NO_FANOUT~
cs[28] => ~NO_FANOUT~
cs[29] => ~NO_FANOUT~
cs[30] => ~NO_FANOUT~
cs[31] => ~NO_FANOUT~
clk => temp[7].CLK
clk => temp[6].CLK
clk => temp[5].CLK
clk => temp[4].CLK
clk => temp[3].CLK
clk => temp[2].CLK
clk => temp[1].CLK
clk => temp[0].CLK
clk => pc_out[7]~reg0.CLK
clk => pc_out[6]~reg0.CLK
clk => pc_out[5]~reg0.CLK
clk => pc_out[4]~reg0.CLK
clk => pc_out[3]~reg0.CLK
clk => pc_out[2]~reg0.CLK
clk => pc_out[1]~reg0.CLK
clk => pc_out[0]~reg0.CLK
pc_out[0] <= pc_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc_out[1] <= pc_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc_out[2] <= pc_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc_out[3] <= pc_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc_out[4] <= pc_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc_out[5] <= pc_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc_out[6] <= pc_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
pc_out[7] <= pc_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE