cpu.hier_info

用VHDL语言设计简单的CPU

ir_out[1] => Mux7.IN18
ir_out[1] => Mux6.IN18
ir_out[1] => Mux5.IN18
ir_out[1] => Mux4.IN18
ir_out[1] => Mux3.IN18
ir_out[1] => Mux2.IN18
ir_out[1] => Mux1.IN18
ir_out[1] => Mux0.IN18
ir_out[2] => Mux7.IN17
ir_out[2] => Mux6.IN17
ir_out[2] => Mux5.IN17
ir_out[2] => Mux4.IN17
ir_out[2] => Mux3.IN17
ir_out[2] => Mux2.IN17
ir_out[2] => Mux1.IN17
ir_out[2] => Mux0.IN17
ir_out[3] => Mux7.IN16
ir_out[3] => Mux6.IN16
ir_out[3] => Mux5.IN16
ir_out[3] => Mux4.IN16
ir_out[3] => Mux3.IN16
ir_out[3] => Mux2.IN16
ir_out[3] => Mux1.IN16
ir_out[3] => Mux0.IN16
ir_out[4] => Mux7.IN15
ir_out[4] => Mux6.IN15
ir_out[4] => Mux5.IN15
ir_out[4] => Mux4.IN15
ir_out[4] => Mux3.IN15
ir_out[4] => Mux2.IN15
ir_out[4] => Mux1.IN15
ir_out[4] => Mux0.IN15
ir_out[5] => Mux7.IN14
ir_out[5] => Mux6.IN14
ir_out[5] => Mux5.IN14
ir_out[5] => Mux4.IN14
ir_out[5] => Mux3.IN14
ir_out[5] => Mux2.IN14
ir_out[5] => Mux1.IN14
ir_out[5] => Mux0.IN14
ir_out[6] => Mux7.IN13
ir_out[6] => Mux6.IN13
ir_out[6] => Mux5.IN13
ir_out[6] => Mux4.IN13
ir_out[6] => Mux3.IN13
ir_out[6] => Mux2.IN13
ir_out[6] => Mux1.IN13
ir_out[6] => Mux0.IN13
ir_out[7] => Mux7.IN12
ir_out[7] => Mux6.IN12
ir_out[7] => Mux5.IN12
ir_out[7] => Mux4.IN12
ir_out[7] => Mux3.IN12
ir_out[7] => Mux2.IN12
ir_out[7] => Mux1.IN12
ir_out[7] => Mux0.IN12
address_out[0] <= address_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address_out[1] <= address_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address_out[2] <= address_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address_out[3] <= address_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address_out[4] <= address_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address_out[5] <= address_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address_out[6] <= address_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
address_out[7] <= address_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|ir:inst4
mbr_in[0] => ir_out[0]~reg0.DATAIN
mbr_in[1] => ir_out[1]~reg0.DATAIN
mbr_in[2] => ir_out[2]~reg0.DATAIN
mbr_in[3] => ir_out[3]~reg0.DATAIN
mbr_in[4] => ir_out[4]~reg0.DATAIN
mbr_in[5] => ir_out[5]~reg0.DATAIN
mbr_in[6] => ir_out[6]~reg0.DATAIN
mbr_in[7] => ir_out[7]~reg0.DATAIN
cs[0] => ~NO_FANOUT~
cs[1] => ~NO_FANOUT~
cs[2] => ~NO_FANOUT~
cs[3] => ~NO_FANOUT~
cs[4] => ~NO_FANOUT~
cs[5] => ~NO_FANOUT~
cs[6] => ~NO_FANOUT~
cs[7] => ir_out[7]~reg0.ENA
cs[7] => ir_out[6]~reg0.ENA
cs[7] => ir_out[5]~reg0.ENA
cs[7] => ir_out[4]~reg0.ENA
cs[7] => ir_out[3]~reg0.ENA
cs[7] => ir_out[2]~reg0.ENA
cs[7] => ir_out[1]~reg0.ENA
cs[7] => ir_out[0]~reg0.ENA
cs[8] => ~NO_FANOUT~
cs[9] => ~NO_FANOUT~
cs[10] => ~NO_FANOUT~
cs[11] => ~NO_FANOUT~
cs[12] => ~NO_FANOUT~
cs[13] => ~NO_FANOUT~
cs[14] => ~NO_FANOUT~
cs[15] => ~NO_FANOUT~
cs[16] => ~NO_FANOUT~
cs[17] => ~NO_FANOUT~
cs[18] => ~NO_FANOUT~
cs[19] => ~NO_FANOUT~
cs[20] => ~NO_FANOUT~
cs[21] => ~NO_FANOUT~
cs[22] => ~NO_FANOUT~
cs[23] => ~NO_FANOUT~
cs[24] => ~NO_FANOUT~
cs[25] => ~NO_FANOUT~
cs[26] => ~NO_FANOUT~
cs[27] => ~NO_FANOUT~
cs[28] => ~NO_FANOUT~
cs[29] => ~NO_FANOUT~
cs[30] => ~NO_FANOUT~
cs[31] => ~NO_FANOUT~
clk => ir_out[7]~reg0.CLK
clk => ir_out[6]~reg0.CLK
clk => ir_out[5]~reg0.CLK
clk => ir_out[4]~reg0.CLK
clk => ir_out[3]~reg0.CLK
clk => ir_out[2]~reg0.CLK
clk => ir_out[1]~reg0.CLK
clk => ir_out[0]~reg0.CLK
ir_out[0] <= ir_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ir_out[1] <= ir_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ir_out[2] <= ir_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ir_out[3] <= ir_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ir_out[4] <= ir_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ir_out[5] <= ir_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ir_out[6] <= ir_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
ir_out[7] <= ir_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|mbr:inst3
acc_in[0] => mbr_out~15.DATAB
acc_in[1] => mbr_out~14.DATAB
acc_in[2] => mbr_out~13.DATAB
acc_in[3] => mbr_out~12.DATAB
acc_in[4] => mbr_out~11.DATAB
acc_in[5] => mbr_out~10.DATAB
acc_in[6] => mbr_out~9.DATAB
acc_in[7] => mbr_out~8.DATAB
acc_in[8] => mbr_out~7.DATAB
acc_in[9] => mbr_out~6.DATAB
acc_in[10] => mbr_out~5.DATAB
acc_in[11] => mbr_out~4.DATAB
acc_in[12] => mbr_out~3.DATAB
acc_in[13] => mbr_out~2.DATAB
acc_in[14] => mbr_out~1.DATAB
acc_in[15] => mbr_out~0.DATAB
memory_in[0] => mbr_out~31.DATAB
memory_in[1] => mbr_out~30.DATAB
memory_in[2] => mbr_out~29.DATAB
memory_in[3] => mbr_out~28.DATAB
memory_in[4] => mbr_out~27.DATAB
memory_in[5] => mbr_out~26.DATAB
memory_in[6] => mbr_out~25.DATAB
memory_in[7] => mbr_out~24.DATAB
memory_in[8] => mbr_out~23.DATAB
memory_in[9] => mbr_out~22.DATAB
memory_in[10] => mbr_out~21.DATAB
memory_in[11] => mbr_out~20.DATAB
memory_in[12] => mbr_out~19.DATAB
memory_in[13] => mbr_out~18.DATAB
memory_in[14] => mbr_out~17.DATAB
memory_in[15] => mbr_out~16.DATAB
cs[0] => ~NO_FANOUT~
cs[1] => ~NO_FANOUT~
cs[2] => ~NO_FANOUT~
cs[3] => ~NO_FANOUT~
cs[4] => ~NO_FANOUT~
cs[5] => ~NO_FANOUT~
cs[6] => ~NO_FANOUT~
cs[7] => ~NO_FANOUT~
cs[8] => ~NO_FANOUT~
cs[9] => ~NO_FANOUT~
cs[10] => ~NO_FANOUT~
cs[11] => ~NO_FANOUT~
cs[12] => ~NO_FANOUT~
cs[13] => ~NO_FANOUT~
cs[14] => ~NO_FANOUT~
cs[15] => mbr_out~31.OUTPUTSELECT
cs[15] => mbr_out~30.OUTPUTSELECT
cs[15] => mbr_out~29.OUTPUTSELECT
cs[15] => mbr_out~28.OUTPUTSELECT
cs[15] => mbr_out~27.OUTPUTSELECT
cs[15] => mbr_out~26.OUTPUTSELECT
cs[15] => mbr_out~25.OUTPUTSELECT
cs[15] => mbr_out~24.OUTPUTSELECT
cs[15] => mbr_out~23.OUTPUTSELECT
cs[15] => mbr_out~22.OUTPUTSELECT
cs[15] => mbr_out~21.OUTPUTSELECT
cs[15] => mbr_out~20.OUTPUTSELECT
cs[15] => mbr_out~19.OUTPUTSELECT
cs[15] => mbr_out~18.OUTPUTSELECT
cs[15] => mbr_out~17.OUTPUTSELECT
cs[15] => mbr_out~16.OUTPUTSELECT
cs[16] => mbr_out~15.OUTPUTSELECT
cs[16] => mbr_out~14.OUTPUTSELECT
cs[16] => mbr_out~13.OUTPUTSELECT
cs[16] => mbr_out~12.OUTPUTSELECT
cs[16] => mbr_out~11.OUTPUTSELECT
cs[16] => mbr_out~10.OUTPUTSELECT
cs[16] => mbr_out~9.OUTPUTSELECT
cs[16] => mbr_out~8.OUTPUTSELECT
cs[16] => mbr_out~7.OUTPUTSELECT
cs[16] => mbr_out~6.OUTPUTSELECT
cs[16] => mbr_out~5.OUTPUTSELECT
cs[16] => mbr_out~4.OUTPUTSELECT
cs[16] => mbr_out~3.OUTPUTSELECT
cs[16] => mbr_out~2.OUTPUTSELECT
cs[16] => mbr_out~1.OUTPUTSELECT
cs[16] => mbr_out~0.OUTPUTSELECT
cs[17] => ~NO_FANOUT~
cs[18] => ~NO_FANOUT~
cs[19] => ~NO_FANOUT~
cs[20] => ~NO_FANOUT~
cs[21] => ~NO_FANOUT~
cs[22] => ~NO_FANOUT~
cs[23] => ~NO_FANOUT~
cs[24] => ~NO_FANOUT~
cs[25] => ~NO_FANOUT~
cs[26] => ~NO_FANOUT~
cs[27] => ~NO_FANOUT~
cs[28] => ~NO_FANOUT~
cs[29] => ~NO_FANOUT~
cs[30] => ~NO_FANOUT~
cs[31] => ~NO_FANOUT~
clk => mbr_out[15]~reg0.CLK
clk => mbr_out[14]~reg0.CLK
clk => mbr_out[13]~reg0.CLK
clk => mbr_out[12]~reg0.CLK
clk => mbr_out[11]~reg0.CLK
clk => mbr_out[10]~reg0.CLK
clk => mbr_out[9]~reg0.CLK
clk => mbr_out[8]~reg0.CLK
clk => mbr_out[7]~reg0.CLK
clk => mbr_out[6]~reg0.CLK
clk => mbr_out[5]~reg0.CLK
clk => mbr_out[4]~reg0.CLK
clk => mbr_out[3]~reg0.CLK
clk => mbr_out[2]~reg0.CLK
clk => mbr_out[1]~reg0.CLK
clk => mbr_out[0]~reg0.CLK
mbr_out[0] <= mbr_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mbr_out[1] <= mbr_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mbr_out[2] <= mbr_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mbr_out[3] <= mbr_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mbr_out[4] <= mbr_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mbr_out[5] <= mbr_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mbr_out[6] <= mbr_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mbr_out[7] <= mbr_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mbr_out[8] <= mbr_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mbr_out[9] <= mbr_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mbr_out[10] <= mbr_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mbr_out[11] <= mbr_out[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mbr_out[12] <= mbr_out[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mbr_out[13] <= mbr_out[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mbr_out[14] <= mbr_out[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
mbr_out[15] <= mbr_out[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|lpm_ram_dq0:inst7
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
data[0] => altsyncram:altsyncram_component.data_a[0]
data[1] => altsyncram:altsyncram_component.data_a[1]
data[2] => altsyncram:altsyncram_component.data_a[2]
data[3] => altsyncram:altsyncram_component.data_a[3]
data[4] => altsyncram:altsyncram_component.data_a[4]
data[5] => altsyncram:altsyncram_component.data_a[5]
data[6] => altsyncram:altsyncram_component.data_a[6]
data[7] => altsyncram:altsyncram_component.data_a[7]
data[8] => altsyncram:altsyncram_component.data_a[8]
data[9] => altsyncram:altsyncram_component.data_a[9]
data[10] => altsyncram:altsyncram_component.data_a[10]
data[11] => altsyncram:altsyncram_component.data_a[11]
data[12] => altsyncram:altsyncram_component.data_a[12]
data[13] => altsyncram:altsyncram_component.data_a[13]
data[14] => altsyncram:altsyncram_component.data_a[14]
data[15] => altsyncram:altsyncram_component.data_a[15]
wren => altsyncram:altsyncram_component.wren_a
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]
q[10] <= altsyncram:altsyncram_component.q_a[10]
q[11] <= altsyncram:altsyncram_component.q_a[11]
q[12] <= altsyncram:altsyncram_component.q_a[12]
q[13] <= altsyncram:altsyncram_component.q_a[13]
q[14] <= altsyncram:altsyncram_component.q_a[14]
q[15] <= altsyncram:altsyncram_component.q_a[15]


|cpu|lpm_ram_dq0:inst7|altsyncram:altsyncram_component
wren_a => altsyncram_3ac1:auto_generated.wren_a
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => altsyncram_3ac1:auto_generated.data_a[0]
data_a[1] => altsyncram_3ac1:auto_generated.data_a[1]
data_a[2] => altsyncram_3ac1:auto_generated.data_a[2]
data_a[3] => altsyncram_3ac1:auto_generated.data_a[3]
data_a[4] => altsyncram_3ac1:auto_generated.data_a[4]
data_a[5] => altsyncram_3ac1:auto_generated.data_a[5]
data_a[6] => altsyncram_3ac1:auto_generated.data_a[6]
data_a[7] => altsyncram_3ac1:auto_generated.data_a[7]
data_a[8] => altsyncram_3ac1:auto_generated.data_a[8]
data_a[9] => altsyncram_3ac1:auto_generated.data_a[9]
data_a[10] => altsyncram_3ac1:auto_generated.data_a[10]
data_a[11] => altsyncram_3ac1:auto_generated.data_a[11]
data_a[12] => altsyncram_3ac1:auto_generated.data_a[12]
data_a[13] => altsyncram_3ac1:auto_generated.data_a[13]
data_a[14] => altsyncram_3ac1:auto_generated.data_a[14]
data_a[15] => altsyncram_3ac1:auto_generated.data_a[15]
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_3ac1:auto_generated.address_a[0]
address_a[1] => altsyncram_3ac1:auto_generated.address_a[1]
address_a[2] => altsyncram_3ac1:auto_generated.address_a[2]
address_a[3] => altsyncram_3ac1:auto_generated.address_a[3]
address_a[4] => altsyncram_3ac1:auto_generated.address_a[4]
address_a[5] => altsyncram_3ac1:auto_generated.address_a[5]
address_a[6] => altsyncram_3ac1:auto_generated.address_a[6]
address_a[7] => altsyncram_3ac1:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_3ac1:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_3ac1:auto_generated.q_a[0]
q_a[1] <= altsyncram_3ac1:auto_generated.q_a[1]
q_a[2] <= altsyncram_3ac1:auto_generated.q_a[2]
q_a[3] <= altsyncram_3ac1:auto_generated.q_a[3]
q_a[4] <= altsyncram_3ac1:auto_generated.q_a[4]
q_a[5] <= altsyncram_3ac1:auto_generated.q_a[5]
q_a[6] <= altsyncram_3ac1:auto_generated.q_a[6]
q_a[7] <= altsyncram_3ac1:auto_generated.q_a[7]
q_a[8] <= altsyncram_3ac1:auto_generated.q_a[8]
q_a[9] <= altsyncram_3ac1:auto_generated.q_a[9]
q_a[10] <= altsyncram_3ac1:auto_generated.q_a[10]
q_a[11] <= altsyncram_3ac1:auto_generated.q_a[11]
q_a[12] <= altsyncram_3ac1:auto_generated.q_a[12]
q_a[13] <= altsyncram_3ac1:auto_generated.q_a[13]
q_a[14] <= altsyncram_3ac1:auto_generated.q_a[14]
q_a[15] <= altsyncram_3ac1:auto_generated.q_a[15]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>