cpu.hier_info

用VHDL语言设计简单的CPU

cs[25] => temp~108.OUTPUTSELECT
cs[25] => temp~107.OUTPUTSELECT
cs[25] => temp~106.OUTPUTSELECT
cs[25] => temp~105.OUTPUTSELECT
cs[25] => temp~104.OUTPUTSELECT
cs[25] => temp~103.OUTPUTSELECT
cs[25] => temp~102.OUTPUTSELECT
cs[25] => temp~101.OUTPUTSELECT
cs[25] => temp~100.OUTPUTSELECT
cs[25] => temp~99.OUTPUTSELECT
cs[25] => temp~98.OUTPUTSELECT
cs[25] => temp~97.OUTPUTSELECT
cs[25] => temp~96.OUTPUTSELECT
cs[26] => ~NO_FANOUT~
cs[27] => ~NO_FANOUT~
cs[28] => ~NO_FANOUT~
cs[29] => ~NO_FANOUT~
cs[30] => ~NO_FANOUT~
cs[31] => ~NO_FANOUT~
clk => temp[15].CLK
clk => temp[14].CLK
clk => temp[13].CLK
clk => temp[12].CLK
clk => temp[11].CLK
clk => temp[10].CLK
clk => temp[9].CLK
clk => temp[8].CLK
clk => temp[7].CLK
clk => temp[6].CLK
clk => temp[5].CLK
clk => temp[4].CLK
clk => temp[3].CLK
clk => temp[2].CLK
clk => temp[1].CLK
clk => temp[0].CLK
clk => acc[15]~reg0.CLK
clk => acc[14]~reg0.CLK
clk => acc[13]~reg0.CLK
clk => acc[12]~reg0.CLK
clk => acc[11]~reg0.CLK
clk => acc[10]~reg0.CLK
clk => acc[9]~reg0.CLK
clk => acc[8]~reg0.CLK
clk => acc[7]~reg0.CLK
clk => acc[6]~reg0.CLK
clk => acc[5]~reg0.CLK
clk => acc[4]~reg0.CLK
clk => acc[3]~reg0.CLK
clk => acc[2]~reg0.CLK
clk => acc[1]~reg0.CLK
clk => acc[0]~reg0.CLK
accis0 <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
acc[0] <= acc[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
acc[1] <= acc[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
acc[2] <= acc[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
acc[3] <= acc[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
acc[4] <= acc[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
acc[5] <= acc[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
acc[6] <= acc[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
acc[7] <= acc[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
acc[8] <= acc[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
acc[9] <= acc[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
acc[10] <= acc[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
acc[11] <= acc[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
acc[12] <= acc[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
acc[13] <= acc[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
acc[14] <= acc[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
acc[15] <= acc[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|br:inst1
mbr_in[0] => br_out[0]~reg0.DATAIN
mbr_in[1] => br_out[1]~reg0.DATAIN
mbr_in[2] => br_out[2]~reg0.DATAIN
mbr_in[3] => br_out[3]~reg0.DATAIN
mbr_in[4] => br_out[4]~reg0.DATAIN
mbr_in[5] => br_out[5]~reg0.DATAIN
mbr_in[6] => br_out[6]~reg0.DATAIN
mbr_in[7] => br_out[7]~reg0.DATAIN
mbr_in[8] => br_out[8]~reg0.DATAIN
mbr_in[9] => br_out[9]~reg0.DATAIN
mbr_in[10] => br_out[10]~reg0.DATAIN
mbr_in[11] => br_out[11]~reg0.DATAIN
mbr_in[12] => br_out[12]~reg0.DATAIN
mbr_in[13] => br_out[13]~reg0.DATAIN
mbr_in[14] => br_out[14]~reg0.DATAIN
mbr_in[15] => br_out[15]~reg0.DATAIN
cs[0] => ~NO_FANOUT~
cs[1] => ~NO_FANOUT~
cs[2] => ~NO_FANOUT~
cs[3] => ~NO_FANOUT~
cs[4] => ~NO_FANOUT~
cs[5] => ~NO_FANOUT~
cs[6] => ~NO_FANOUT~
cs[7] => ~NO_FANOUT~
cs[8] => ~NO_FANOUT~
cs[9] => ~NO_FANOUT~
cs[10] => ~NO_FANOUT~
cs[11] => ~NO_FANOUT~
cs[12] => ~NO_FANOUT~
cs[13] => ~NO_FANOUT~
cs[14] => ~NO_FANOUT~
cs[15] => ~NO_FANOUT~
cs[16] => ~NO_FANOUT~
cs[17] => ~NO_FANOUT~
cs[18] => ~NO_FANOUT~
cs[19] => ~NO_FANOUT~
cs[20] => ~NO_FANOUT~
cs[21] => br_out[7]~reg0.ENA
cs[21] => br_out[6]~reg0.ENA
cs[21] => br_out[5]~reg0.ENA
cs[21] => br_out[4]~reg0.ENA
cs[21] => br_out[3]~reg0.ENA
cs[21] => br_out[2]~reg0.ENA
cs[21] => br_out[1]~reg0.ENA
cs[21] => br_out[0]~reg0.ENA
cs[21] => br_out[8]~reg0.ENA
cs[21] => br_out[9]~reg0.ENA
cs[21] => br_out[10]~reg0.ENA
cs[21] => br_out[11]~reg0.ENA
cs[21] => br_out[12]~reg0.ENA
cs[21] => br_out[13]~reg0.ENA
cs[21] => br_out[14]~reg0.ENA
cs[21] => br_out[15]~reg0.ENA
cs[22] => ~NO_FANOUT~
cs[23] => ~NO_FANOUT~
cs[24] => ~NO_FANOUT~
cs[25] => ~NO_FANOUT~
cs[26] => ~NO_FANOUT~
cs[27] => ~NO_FANOUT~
cs[28] => ~NO_FANOUT~
cs[29] => ~NO_FANOUT~
cs[30] => ~NO_FANOUT~
cs[31] => ~NO_FANOUT~
clk => br_out[15]~reg0.CLK
clk => br_out[14]~reg0.CLK
clk => br_out[13]~reg0.CLK
clk => br_out[12]~reg0.CLK
clk => br_out[11]~reg0.CLK
clk => br_out[10]~reg0.CLK
clk => br_out[9]~reg0.CLK
clk => br_out[8]~reg0.CLK
clk => br_out[7]~reg0.CLK
clk => br_out[6]~reg0.CLK
clk => br_out[5]~reg0.CLK
clk => br_out[4]~reg0.CLK
clk => br_out[3]~reg0.CLK
clk => br_out[2]~reg0.CLK
clk => br_out[1]~reg0.CLK
clk => br_out[0]~reg0.CLK
br_out[0] <= br_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
br_out[1] <= br_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
br_out[2] <= br_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
br_out[3] <= br_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
br_out[4] <= br_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
br_out[5] <= br_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
br_out[6] <= br_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
br_out[7] <= br_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
br_out[8] <= br_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
br_out[9] <= br_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
br_out[10] <= br_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
br_out[11] <= br_out[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
br_out[12] <= br_out[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
br_out[13] <= br_out[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
br_out[14] <= br_out[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
br_out[15] <= br_out[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|cpu|lpm_rom0:inst8
address[0] => altsyncram:altsyncram_component.address_a[0]
address[1] => altsyncram:altsyncram_component.address_a[1]
address[2] => altsyncram:altsyncram_component.address_a[2]
address[3] => altsyncram:altsyncram_component.address_a[3]
address[4] => altsyncram:altsyncram_component.address_a[4]
address[5] => altsyncram:altsyncram_component.address_a[5]
address[6] => altsyncram:altsyncram_component.address_a[6]
address[7] => altsyncram:altsyncram_component.address_a[7]
clock => altsyncram:altsyncram_component.clock0
q[0] <= altsyncram:altsyncram_component.q_a[0]
q[1] <= altsyncram:altsyncram_component.q_a[1]
q[2] <= altsyncram:altsyncram_component.q_a[2]
q[3] <= altsyncram:altsyncram_component.q_a[3]
q[4] <= altsyncram:altsyncram_component.q_a[4]
q[5] <= altsyncram:altsyncram_component.q_a[5]
q[6] <= altsyncram:altsyncram_component.q_a[6]
q[7] <= altsyncram:altsyncram_component.q_a[7]
q[8] <= altsyncram:altsyncram_component.q_a[8]
q[9] <= altsyncram:altsyncram_component.q_a[9]
q[10] <= altsyncram:altsyncram_component.q_a[10]
q[11] <= altsyncram:altsyncram_component.q_a[11]
q[12] <= altsyncram:altsyncram_component.q_a[12]
q[13] <= altsyncram:altsyncram_component.q_a[13]
q[14] <= altsyncram:altsyncram_component.q_a[14]
q[15] <= altsyncram:altsyncram_component.q_a[15]
q[16] <= altsyncram:altsyncram_component.q_a[16]
q[17] <= altsyncram:altsyncram_component.q_a[17]
q[18] <= altsyncram:altsyncram_component.q_a[18]
q[19] <= altsyncram:altsyncram_component.q_a[19]
q[20] <= altsyncram:altsyncram_component.q_a[20]
q[21] <= altsyncram:altsyncram_component.q_a[21]
q[22] <= altsyncram:altsyncram_component.q_a[22]
q[23] <= altsyncram:altsyncram_component.q_a[23]
q[24] <= altsyncram:altsyncram_component.q_a[24]
q[25] <= altsyncram:altsyncram_component.q_a[25]
q[26] <= altsyncram:altsyncram_component.q_a[26]
q[27] <= altsyncram:altsyncram_component.q_a[27]
q[28] <= altsyncram:altsyncram_component.q_a[28]
q[29] <= altsyncram:altsyncram_component.q_a[29]
q[30] <= altsyncram:altsyncram_component.q_a[30]
q[31] <= altsyncram:altsyncram_component.q_a[31]


|cpu|lpm_rom0:inst8|altsyncram:altsyncram_component
wren_a => ~NO_FANOUT~
rden_a => ~NO_FANOUT~
wren_b => ~NO_FANOUT~
rden_b => ~NO_FANOUT~
data_a[0] => ~NO_FANOUT~
data_a[1] => ~NO_FANOUT~
data_a[2] => ~NO_FANOUT~
data_a[3] => ~NO_FANOUT~
data_a[4] => ~NO_FANOUT~
data_a[5] => ~NO_FANOUT~
data_a[6] => ~NO_FANOUT~
data_a[7] => ~NO_FANOUT~
data_a[8] => ~NO_FANOUT~
data_a[9] => ~NO_FANOUT~
data_a[10] => ~NO_FANOUT~
data_a[11] => ~NO_FANOUT~
data_a[12] => ~NO_FANOUT~
data_a[13] => ~NO_FANOUT~
data_a[14] => ~NO_FANOUT~
data_a[15] => ~NO_FANOUT~
data_a[16] => ~NO_FANOUT~
data_a[17] => ~NO_FANOUT~
data_a[18] => ~NO_FANOUT~
data_a[19] => ~NO_FANOUT~
data_a[20] => ~NO_FANOUT~
data_a[21] => ~NO_FANOUT~
data_a[22] => ~NO_FANOUT~
data_a[23] => ~NO_FANOUT~
data_a[24] => ~NO_FANOUT~
data_a[25] => ~NO_FANOUT~
data_a[26] => ~NO_FANOUT~
data_a[27] => ~NO_FANOUT~
data_a[28] => ~NO_FANOUT~
data_a[29] => ~NO_FANOUT~
data_a[30] => ~NO_FANOUT~
data_a[31] => ~NO_FANOUT~
data_b[0] => ~NO_FANOUT~
address_a[0] => altsyncram_js61:auto_generated.address_a[0]
address_a[1] => altsyncram_js61:auto_generated.address_a[1]
address_a[2] => altsyncram_js61:auto_generated.address_a[2]
address_a[3] => altsyncram_js61:auto_generated.address_a[3]
address_a[4] => altsyncram_js61:auto_generated.address_a[4]
address_a[5] => altsyncram_js61:auto_generated.address_a[5]
address_a[6] => altsyncram_js61:auto_generated.address_a[6]
address_a[7] => altsyncram_js61:auto_generated.address_a[7]
address_b[0] => ~NO_FANOUT~
addressstall_a => ~NO_FANOUT~
addressstall_b => ~NO_FANOUT~
clock0 => altsyncram_js61:auto_generated.clock0
clock1 => ~NO_FANOUT~
clocken0 => ~NO_FANOUT~
clocken1 => ~NO_FANOUT~
clocken2 => ~NO_FANOUT~
clocken3 => ~NO_FANOUT~
aclr0 => ~NO_FANOUT~
aclr1 => ~NO_FANOUT~
byteena_a[0] => ~NO_FANOUT~
byteena_b[0] => ~NO_FANOUT~
q_a[0] <= altsyncram_js61:auto_generated.q_a[0]
q_a[1] <= altsyncram_js61:auto_generated.q_a[1]
q_a[2] <= altsyncram_js61:auto_generated.q_a[2]
q_a[3] <= altsyncram_js61:auto_generated.q_a[3]
q_a[4] <= altsyncram_js61:auto_generated.q_a[4]
q_a[5] <= altsyncram_js61:auto_generated.q_a[5]
q_a[6] <= altsyncram_js61:auto_generated.q_a[6]
q_a[7] <= altsyncram_js61:auto_generated.q_a[7]
q_a[8] <= altsyncram_js61:auto_generated.q_a[8]
q_a[9] <= altsyncram_js61:auto_generated.q_a[9]
q_a[10] <= altsyncram_js61:auto_generated.q_a[10]
q_a[11] <= altsyncram_js61:auto_generated.q_a[11]
q_a[12] <= altsyncram_js61:auto_generated.q_a[12]
q_a[13] <= altsyncram_js61:auto_generated.q_a[13]
q_a[14] <= altsyncram_js61:auto_generated.q_a[14]
q_a[15] <= altsyncram_js61:auto_generated.q_a[15]
q_a[16] <= altsyncram_js61:auto_generated.q_a[16]
q_a[17] <= altsyncram_js61:auto_generated.q_a[17]
q_a[18] <= altsyncram_js61:auto_generated.q_a[18]
q_a[19] <= altsyncram_js61:auto_generated.q_a[19]
q_a[20] <= altsyncram_js61:auto_generated.q_a[20]
q_a[21] <= altsyncram_js61:auto_generated.q_a[21]
q_a[22] <= altsyncram_js61:auto_generated.q_a[22]
q_a[23] <= altsyncram_js61:auto_generated.q_a[23]
q_a[24] <= altsyncram_js61:auto_generated.q_a[24]
q_a[25] <= altsyncram_js61:auto_generated.q_a[25]
q_a[26] <= altsyncram_js61:auto_generated.q_a[26]
q_a[27] <= altsyncram_js61:auto_generated.q_a[27]
q_a[28] <= altsyncram_js61:auto_generated.q_a[28]
q_a[29] <= altsyncram_js61:auto_generated.q_a[29]
q_a[30] <= altsyncram_js61:auto_generated.q_a[30]
q_a[31] <= altsyncram_js61:auto_generated.q_a[31]
q_b[0] <= <GND>
eccstatus[0] <= <GND>
eccstatus[1] <= <GND>
eccstatus[2] <= <GND>


|cpu|lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated
address_a[0] => ram_block1a0.PORTAADDR
address_a[0] => ram_block1a1.PORTAADDR
address_a[0] => ram_block1a2.PORTAADDR
address_a[0] => ram_block1a3.PORTAADDR
address_a[0] => ram_block1a4.PORTAADDR
address_a[0] => ram_block1a5.PORTAADDR
address_a[0] => ram_block1a6.PORTAADDR
address_a[0] => ram_block1a7.PORTAADDR
address_a[0] => ram_block1a8.PORTAADDR
address_a[0] => ram_block1a9.PORTAADDR
address_a[0] => ram_block1a10.PORTAADDR
address_a[0] => ram_block1a11.PORTAADDR
address_a[0] => ram_block1a12.PORTAADDR
address_a[0] => ram_block1a13.PORTAADDR
address_a[0] => ram_block1a14.PORTAADDR
address_a[0] => ram_block1a15.PORTAADDR
address_a[0] => ram_block1a16.PORTAADDR
address_a[0] => ram_block1a17.PORTAADDR
address_a[0] => ram_block1a18.PORTAADDR
address_a[0] => ram_block1a19.PORTAADDR
address_a[0] => ram_block1a20.PORTAADDR
address_a[0] => ram_block1a21.PORTAADDR
address_a[0] => ram_block1a22.PORTAADDR
address_a[0] => ram_block1a23.PORTAADDR
address_a[0] => ram_block1a24.PORTAADDR
address_a[0] => ram_block1a25.PORTAADDR
address_a[0] => ram_block1a26.PORTAADDR
address_a[0] => ram_block1a27.PORTAADDR
address_a[0] => ram_block1a28.PORTAADDR
address_a[0] => ram_block1a29.PORTAADDR
address_a[0] => ram_block1a30.PORTAADDR
address_a[0] => ram_block1a31.PORTAADDR
address_a[1] => ram_block1a0.PORTAADDR1
address_a[1] => ram_block1a1.PORTAADDR1
address_a[1] => ram_block1a2.PORTAADDR1
address_a[1] => ram_block1a3.PORTAADDR1
address_a[1] => ram_block1a4.PORTAADDR1
address_a[1] => ram_block1a5.PORTAADDR1
address_a[1] => ram_block1a6.PORTAADDR1
address_a[1] => ram_block1a7.PORTAADDR1
address_a[1] => ram_block1a8.PORTAADDR1
address_a[1] => ram_block1a9.PORTAADDR1
address_a[1] => ram_block1a10.PORTAADDR1
address_a[1] => ram_block1a11.PORTAADDR1
address_a[1] => ram_block1a12.PORTAADDR1
address_a[1] => ram_block1a13.PORTAADDR1
address_a[1] => ram_block1a14.PORTAADDR1
address_a[1] => ram_block1a15.PORTAADDR1
address_a[1] => ram_block1a16.PORTAADDR1
address_a[1] => ram_block1a17.PORTAADDR1
address_a[1] => ram_block1a18.PORTAADDR1
address_a[1] => ram_block1a19.PORTAADDR1
address_a[1] => ram_block1a20.PORTAADDR1
address_a[1] => ram_block1a21.PORTAADDR1
address_a[1] => ram_block1a22.PORTAADDR1
address_a[1] => ram_block1a23.PORTAADDR1
address_a[1] => ram_block1a24.PORTAADDR1
address_a[1] => ram_block1a25.PORTAADDR1