cpu.hier_info

用VHDL语言设计简单的CPU

|cpu
acc[0] <= alu:inst.acc[0]
acc[1] <= alu:inst.acc[1]
acc[2] <= alu:inst.acc[2]
acc[3] <= alu:inst.acc[3]
acc[4] <= alu:inst.acc[4]
acc[5] <= alu:inst.acc[5]
acc[6] <= alu:inst.acc[6]
acc[7] <= alu:inst.acc[7]
acc[8] <= alu:inst.acc[8]
acc[9] <= alu:inst.acc[9]
acc[10] <= alu:inst.acc[10]
acc[11] <= alu:inst.acc[11]
acc[12] <= alu:inst.acc[12]
acc[13] <= alu:inst.acc[13]
acc[14] <= alu:inst.acc[14]
acc[15] <= alu:inst.acc[15]
clk => alu:inst.clk
clk => br:inst1.clk
clk => lpm_rom0:inst8.clock
clk => control_unit:inst2.clk
clk => ir:inst4.clk
clk => mbr:inst3.clk
clk => mar:inst6.clk
clk => pc:inst5.clk
br[0] <= br:inst1.br_out[0]
br[1] <= br:inst1.br_out[1]
br[2] <= br:inst1.br_out[2]
br[3] <= br:inst1.br_out[3]
br[4] <= br:inst1.br_out[4]
br[5] <= br:inst1.br_out[5]
br[6] <= br:inst1.br_out[6]
br[7] <= br:inst1.br_out[7]
br[8] <= br:inst1.br_out[8]
br[9] <= br:inst1.br_out[9]
br[10] <= br:inst1.br_out[10]
br[11] <= br:inst1.br_out[11]
br[12] <= br:inst1.br_out[12]
br[13] <= br:inst1.br_out[13]
br[14] <= br:inst1.br_out[14]
br[15] <= br:inst1.br_out[15]
cs[0] <= lpm_rom0:inst8.q[0]
cs[1] <= lpm_rom0:inst8.q[1]
cs[2] <= lpm_rom0:inst8.q[2]
cs[3] <= lpm_rom0:inst8.q[3]
cs[4] <= lpm_rom0:inst8.q[4]
cs[5] <= lpm_rom0:inst8.q[5]
cs[6] <= lpm_rom0:inst8.q[6]
cs[7] <= lpm_rom0:inst8.q[7]
cs[8] <= lpm_rom0:inst8.q[8]
cs[9] <= lpm_rom0:inst8.q[9]
cs[10] <= lpm_rom0:inst8.q[10]
cs[11] <= lpm_rom0:inst8.q[11]
cs[12] <= lpm_rom0:inst8.q[12]
cs[13] <= lpm_rom0:inst8.q[13]
cs[14] <= lpm_rom0:inst8.q[14]
cs[15] <= lpm_rom0:inst8.q[15]
cs[16] <= lpm_rom0:inst8.q[16]
cs[17] <= lpm_rom0:inst8.q[17]
cs[18] <= lpm_rom0:inst8.q[18]
cs[19] <= lpm_rom0:inst8.q[19]
cs[20] <= lpm_rom0:inst8.q[20]
cs[21] <= lpm_rom0:inst8.q[21]
cs[22] <= lpm_rom0:inst8.q[22]
cs[23] <= lpm_rom0:inst8.q[23]
cs[24] <= lpm_rom0:inst8.q[24]
cs[25] <= lpm_rom0:inst8.q[25]
cs[26] <= lpm_rom0:inst8.q[26]
cs[27] <= lpm_rom0:inst8.q[27]
cs[28] <= lpm_rom0:inst8.q[28]
cs[29] <= lpm_rom0:inst8.q[29]
cs[30] <= lpm_rom0:inst8.q[30]
cs[31] <= lpm_rom0:inst8.q[31]
control_out[0] <= control_unit:inst2.address_out[0]
control_out[1] <= control_unit:inst2.address_out[1]
control_out[2] <= control_unit:inst2.address_out[2]
control_out[3] <= control_unit:inst2.address_out[3]
control_out[4] <= control_unit:inst2.address_out[4]
control_out[5] <= control_unit:inst2.address_out[5]
control_out[6] <= control_unit:inst2.address_out[6]
control_out[7] <= control_unit:inst2.address_out[7]
ir[0] <= ir:inst4.ir_out[0]
ir[1] <= ir:inst4.ir_out[1]
ir[2] <= ir:inst4.ir_out[2]
ir[3] <= ir:inst4.ir_out[3]
ir[4] <= ir:inst4.ir_out[4]
ir[5] <= ir:inst4.ir_out[5]
ir[6] <= ir:inst4.ir_out[6]
ir[7] <= ir:inst4.ir_out[7]
mbr[0] <= mbr:inst3.mbr_out[0]
mbr[1] <= mbr:inst3.mbr_out[1]
mbr[2] <= mbr:inst3.mbr_out[2]
mbr[3] <= mbr:inst3.mbr_out[3]
mbr[4] <= mbr:inst3.mbr_out[4]
mbr[5] <= mbr:inst3.mbr_out[5]
mbr[6] <= mbr:inst3.mbr_out[6]
mbr[7] <= mbr:inst3.mbr_out[7]
mbr[8] <= mbr:inst3.mbr_out[8]
mbr[9] <= mbr:inst3.mbr_out[9]
mbr[10] <= mbr:inst3.mbr_out[10]
mbr[11] <= mbr:inst3.mbr_out[11]
mbr[12] <= mbr:inst3.mbr_out[12]
mbr[13] <= mbr:inst3.mbr_out[13]
mbr[14] <= mbr:inst3.mbr_out[14]
mbr[15] <= mbr:inst3.mbr_out[15]
memory[0] <= lpm_ram_dq0:inst7.q[0]
memory[1] <= lpm_ram_dq0:inst7.q[1]
memory[2] <= lpm_ram_dq0:inst7.q[2]
memory[3] <= lpm_ram_dq0:inst7.q[3]
memory[4] <= lpm_ram_dq0:inst7.q[4]
memory[5] <= lpm_ram_dq0:inst7.q[5]
memory[6] <= lpm_ram_dq0:inst7.q[6]
memory[7] <= lpm_ram_dq0:inst7.q[7]
memory[8] <= lpm_ram_dq0:inst7.q[8]
memory[9] <= lpm_ram_dq0:inst7.q[9]
memory[10] <= lpm_ram_dq0:inst7.q[10]
memory[11] <= lpm_ram_dq0:inst7.q[11]
memory[12] <= lpm_ram_dq0:inst7.q[12]
memory[13] <= lpm_ram_dq0:inst7.q[13]
memory[14] <= lpm_ram_dq0:inst7.q[14]
memory[15] <= lpm_ram_dq0:inst7.q[15]
clock => lpm_ram_dq0:inst7.clock
mar[0] <= mar:inst6.mar_out[0]
mar[1] <= mar:inst6.mar_out[1]
mar[2] <= mar:inst6.mar_out[2]
mar[3] <= mar:inst6.mar_out[3]
mar[4] <= mar:inst6.mar_out[4]
mar[5] <= mar:inst6.mar_out[5]
mar[6] <= mar:inst6.mar_out[6]
mar[7] <= mar:inst6.mar_out[7]
pc[0] <= pc:inst5.pc_out[0]
pc[1] <= pc:inst5.pc_out[1]
pc[2] <= pc:inst5.pc_out[2]
pc[3] <= pc:inst5.pc_out[3]
pc[4] <= pc:inst5.pc_out[4]
pc[5] <= pc:inst5.pc_out[5]
pc[6] <= pc:inst5.pc_out[6]
pc[7] <= pc:inst5.pc_out[7]


|cpu|alu:inst
br_in[0] => temp~94.DATAB
br_in[0] => temp~16.IN1
br_in[0] => temp~0.IN1
br_in[0] => Add0.IN16
br_in[0] => Add1.IN16
br_in[1] => temp~111.DATAB
br_in[1] => temp~93.DATAB
br_in[1] => temp~17.IN1
br_in[1] => temp~1.IN1
br_in[1] => Add0.IN15
br_in[1] => Add1.IN15
br_in[2] => temp~110.DATAB
br_in[2] => temp~92.DATAB
br_in[2] => temp~18.IN1
br_in[2] => temp~2.IN1
br_in[2] => Add0.IN14
br_in[2] => Add1.IN14
br_in[3] => temp~109.DATAB
br_in[3] => temp~91.DATAB
br_in[3] => temp~19.IN1
br_in[3] => temp~3.IN1
br_in[3] => Add0.IN13
br_in[3] => Add1.IN13
br_in[4] => temp~108.DATAB
br_in[4] => temp~90.DATAB
br_in[4] => temp~20.IN1
br_in[4] => temp~4.IN1
br_in[4] => Add0.IN12
br_in[4] => Add1.IN12
br_in[5] => temp~107.DATAB
br_in[5] => temp~89.DATAB
br_in[5] => temp~21.IN1
br_in[5] => temp~5.IN1
br_in[5] => Add0.IN11
br_in[5] => Add1.IN11
br_in[6] => temp~106.DATAB
br_in[6] => temp~88.DATAB
br_in[6] => temp~22.IN1
br_in[6] => temp~6.IN1
br_in[6] => Add0.IN10
br_in[6] => Add1.IN10
br_in[7] => temp~105.DATAB
br_in[7] => temp~87.DATAB
br_in[7] => temp~23.IN1
br_in[7] => temp~7.IN1
br_in[7] => Add0.IN9
br_in[7] => Add1.IN9
br_in[8] => temp~104.DATAB
br_in[8] => temp~86.DATAB
br_in[8] => temp~24.IN1
br_in[8] => temp~8.IN1
br_in[8] => Add0.IN8
br_in[8] => Add1.IN8
br_in[9] => temp~103.DATAB
br_in[9] => temp~85.DATAB
br_in[9] => temp~25.IN1
br_in[9] => temp~9.IN1
br_in[9] => Add0.IN7
br_in[9] => Add1.IN7
br_in[10] => temp~102.DATAB
br_in[10] => temp~84.DATAB
br_in[10] => temp~26.IN1
br_in[10] => temp~10.IN1
br_in[10] => Add0.IN6
br_in[10] => Add1.IN6
br_in[11] => temp~101.DATAB
br_in[11] => temp~83.DATAB
br_in[11] => temp~27.IN1
br_in[11] => temp~11.IN1
br_in[11] => Add0.IN5
br_in[11] => Add1.IN5
br_in[12] => temp~100.DATAB
br_in[12] => temp~82.DATAB
br_in[12] => temp~28.IN1
br_in[12] => temp~12.IN1
br_in[12] => Add0.IN4
br_in[12] => Add1.IN4
br_in[13] => temp~99.DATAB
br_in[13] => temp~81.DATAB
br_in[13] => temp~29.IN1
br_in[13] => temp~13.IN1
br_in[13] => Add0.IN3
br_in[13] => Add1.IN3
br_in[14] => temp~98.DATAB
br_in[14] => temp~80.DATAB
br_in[14] => temp~30.IN1
br_in[14] => temp~14.IN1
br_in[14] => Add0.IN2
br_in[14] => Add1.IN2
br_in[15] => temp~97.DATAB
br_in[15] => temp~31.IN1
br_in[15] => temp~15.IN1
br_in[15] => Add0.IN1
br_in[15] => Add1.IN1
cs[0] => ~NO_FANOUT~
cs[1] => temp~79.OUTPUTSELECT
cs[1] => temp~78.OUTPUTSELECT
cs[1] => temp~77.OUTPUTSELECT
cs[1] => temp~76.OUTPUTSELECT
cs[1] => temp~75.OUTPUTSELECT
cs[1] => temp~74.OUTPUTSELECT
cs[1] => temp~73.OUTPUTSELECT
cs[1] => temp~72.OUTPUTSELECT
cs[1] => temp~71.OUTPUTSELECT
cs[1] => temp~70.OUTPUTSELECT
cs[1] => temp~69.OUTPUTSELECT
cs[1] => temp~68.OUTPUTSELECT
cs[1] => temp~67.OUTPUTSELECT
cs[1] => temp~66.OUTPUTSELECT
cs[1] => temp~65.OUTPUTSELECT
cs[1] => temp~64.OUTPUTSELECT
cs[2] => temp~63.OUTPUTSELECT
cs[2] => temp~62.OUTPUTSELECT
cs[2] => temp~61.OUTPUTSELECT
cs[2] => temp~60.OUTPUTSELECT
cs[2] => temp~59.OUTPUTSELECT
cs[2] => temp~58.OUTPUTSELECT
cs[2] => temp~57.OUTPUTSELECT
cs[2] => temp~56.OUTPUTSELECT
cs[2] => temp~55.OUTPUTSELECT
cs[2] => temp~54.OUTPUTSELECT
cs[2] => temp~53.OUTPUTSELECT
cs[2] => temp~52.OUTPUTSELECT
cs[2] => temp~51.OUTPUTSELECT
cs[2] => temp~50.OUTPUTSELECT
cs[2] => temp~49.OUTPUTSELECT
cs[2] => temp~48.OUTPUTSELECT
cs[3] => temp~47.OUTPUTSELECT
cs[3] => temp~46.OUTPUTSELECT
cs[3] => temp~45.OUTPUTSELECT
cs[3] => temp~44.OUTPUTSELECT
cs[3] => temp~43.OUTPUTSELECT
cs[3] => temp~42.OUTPUTSELECT
cs[3] => temp~41.OUTPUTSELECT
cs[3] => temp~40.OUTPUTSELECT
cs[3] => temp~39.OUTPUTSELECT
cs[3] => temp~38.OUTPUTSELECT
cs[3] => temp~37.OUTPUTSELECT
cs[3] => temp~36.OUTPUTSELECT
cs[3] => temp~35.OUTPUTSELECT
cs[3] => temp~34.OUTPUTSELECT
cs[3] => temp~33.OUTPUTSELECT
cs[3] => temp~32.OUTPUTSELECT
cs[4] => ~NO_FANOUT~
cs[5] => ~NO_FANOUT~
cs[6] => ~NO_FANOUT~
cs[7] => temp~95.OUTPUTSELECT
cs[7] => temp~94.OUTPUTSELECT
cs[7] => temp~93.OUTPUTSELECT
cs[7] => temp~92.OUTPUTSELECT
cs[7] => temp~91.OUTPUTSELECT
cs[7] => temp~90.OUTPUTSELECT
cs[7] => temp~89.OUTPUTSELECT
cs[7] => temp~88.OUTPUTSELECT
cs[7] => temp~87.OUTPUTSELECT
cs[7] => temp~86.OUTPUTSELECT
cs[7] => temp~85.OUTPUTSELECT
cs[7] => temp~84.OUTPUTSELECT
cs[7] => temp~83.OUTPUTSELECT
cs[7] => temp~82.OUTPUTSELECT
cs[7] => temp~81.OUTPUTSELECT
cs[7] => temp~80.OUTPUTSELECT
cs[8] => ~NO_FANOUT~
cs[9] => ~NO_FANOUT~
cs[10] => ~NO_FANOUT~
cs[11] => ~NO_FANOUT~
cs[12] => ~NO_FANOUT~
cs[13] => ~NO_FANOUT~
cs[14] => ~NO_FANOUT~
cs[15] => ~NO_FANOUT~
cs[16] => ~NO_FANOUT~
cs[17] => ~NO_FANOUT~
cs[18] => ~NO_FANOUT~
cs[19] => ~NO_FANOUT~
cs[20] => ~NO_FANOUT~
cs[21] => ~NO_FANOUT~
cs[22] => temp~143.OUTPUTSELECT
cs[22] => temp~142.OUTPUTSELECT
cs[22] => temp~141.OUTPUTSELECT
cs[22] => temp~140.OUTPUTSELECT
cs[22] => temp~139.OUTPUTSELECT
cs[22] => temp~138.OUTPUTSELECT
cs[22] => temp~137.OUTPUTSELECT
cs[22] => temp~136.OUTPUTSELECT
cs[22] => temp~135.OUTPUTSELECT
cs[22] => temp~134.OUTPUTSELECT
cs[22] => temp~133.OUTPUTSELECT
cs[22] => temp~132.OUTPUTSELECT
cs[22] => temp~131.OUTPUTSELECT
cs[22] => temp~130.OUTPUTSELECT
cs[22] => temp~129.OUTPUTSELECT
cs[22] => temp~128.OUTPUTSELECT
cs[23] => temp~127.OUTPUTSELECT
cs[23] => temp~126.OUTPUTSELECT
cs[23] => temp~125.OUTPUTSELECT
cs[23] => temp~124.OUTPUTSELECT
cs[23] => temp~123.OUTPUTSELECT
cs[23] => temp~122.OUTPUTSELECT
cs[23] => temp~121.OUTPUTSELECT
cs[23] => temp~120.OUTPUTSELECT
cs[23] => temp~119.OUTPUTSELECT
cs[23] => temp~118.OUTPUTSELECT
cs[23] => temp~117.OUTPUTSELECT
cs[23] => temp~116.OUTPUTSELECT
cs[23] => temp~115.OUTPUTSELECT
cs[23] => temp~114.OUTPUTSELECT
cs[23] => temp~113.OUTPUTSELECT
cs[23] => temp~112.OUTPUTSELECT
cs[24] => temp~159.OUTPUTSELECT
cs[24] => temp~158.OUTPUTSELECT
cs[24] => temp~157.OUTPUTSELECT
cs[24] => temp~156.OUTPUTSELECT
cs[24] => temp~155.OUTPUTSELECT
cs[24] => temp~154.OUTPUTSELECT
cs[24] => temp~153.OUTPUTSELECT
cs[24] => temp~152.OUTPUTSELECT
cs[24] => temp~151.OUTPUTSELECT
cs[24] => temp~150.OUTPUTSELECT
cs[24] => temp~149.OUTPUTSELECT
cs[24] => temp~148.OUTPUTSELECT
cs[24] => temp~147.OUTPUTSELECT
cs[24] => temp~146.OUTPUTSELECT
cs[24] => temp~145.OUTPUTSELECT
cs[24] => temp~144.OUTPUTSELECT
cs[25] => temp~111.OUTPUTSELECT
cs[25] => temp~110.OUTPUTSELECT
cs[25] => temp~109.OUTPUTSELECT