prev_cmp_cpu.tan.qmsg

用VHDL语言设计简单的CPU

{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register alu:inst\|temp\[12\] register control_unit:inst2\|address\[1\] 267.67 MHz 3.736 ns Internal " "Info: Clock \"clk\" has Internal fmax of 267.67 MHz between source register \"alu:inst\|temp\[12\]\" and destination register \"control_unit:inst2\|address\[1\]\" (period= 3.736 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.561 ns + Longest register register " "Info: + Longest register to register delay is 3.561 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns alu:inst\|temp\[12\] 1 REG LCFF_X7_Y21_N15 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X7_Y21_N15; Fanout = 5; REG Node = 'alu:inst\|temp\[12\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { alu:inst|temp[12] } "NODE_NAME" } } { "alu.vhd" "" { Text "F:/another way/cpu/alu.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.555 ns) + CELL(0.366 ns) 0.921 ns alu:inst\|Equal0~84 2 COMB LCCOMB_X6_Y21_N18 1 " "Info: 2: + IC(0.555 ns) + CELL(0.366 ns) = 0.921 ns; Loc. = LCCOMB_X6_Y21_N18; Fanout = 1; COMB Node = 'alu:inst\|Equal0~84'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.921 ns" { alu:inst|temp[12] alu:inst|Equal0~84 } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.532 ns) + CELL(0.053 ns) 1.506 ns alu:inst\|Equal0~85 3 COMB LCCOMB_X6_Y22_N30 2 " "Info: 3: + IC(0.532 ns) + CELL(0.053 ns) = 1.506 ns; Loc. = LCCOMB_X6_Y22_N30; Fanout = 2; COMB Node = 'alu:inst\|Equal0~85'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.585 ns" { alu:inst|Equal0~84 alu:inst|Equal0~85 } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.545 ns) + CELL(0.053 ns) 2.104 ns control_unit:inst2\|Mux6~742 4 COMB LCCOMB_X6_Y23_N0 1 " "Info: 4: + IC(0.545 ns) + CELL(0.053 ns) = 2.104 ns; Loc. = LCCOMB_X6_Y23_N0; Fanout = 1; COMB Node = 'control_unit:inst2\|Mux6~742'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.598 ns" { alu:inst|Equal0~85 control_unit:inst2|Mux6~742 } "NODE_NAME" } } { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.580 ns) + CELL(0.366 ns) 3.050 ns control_unit:inst2\|Mux6~743 5 COMB LCCOMB_X7_Y23_N16 2 " "Info: 5: + IC(0.580 ns) + CELL(0.366 ns) = 3.050 ns; Loc. = LCCOMB_X7_Y23_N16; Fanout = 2; COMB Node = 'control_unit:inst2\|Mux6~743'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.946 ns" { control_unit:inst2|Mux6~742 control_unit:inst2|Mux6~743 } "NODE_NAME" } } { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.202 ns) + CELL(0.309 ns) 3.561 ns control_unit:inst2\|address\[1\] 6 REG LCFF_X7_Y23_N3 3 " "Info: 6: + IC(0.202 ns) + CELL(0.309 ns) = 3.561 ns; Loc. = LCFF_X7_Y23_N3; Fanout = 3; REG Node = 'control_unit:inst2\|address\[1\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.511 ns" { control_unit:inst2|Mux6~743 control_unit:inst2|address[1] } "NODE_NAME" } } { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.147 ns ( 32.21 % ) " "Info: Total cell delay = 1.147 ns ( 32.21 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.414 ns ( 67.79 % ) " "Info: Total interconnect delay = 2.414 ns ( 67.79 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.561 ns" { alu:inst|temp[12] alu:inst|Equal0~84 alu:inst|Equal0~85 control_unit:inst2|Mux6~742 control_unit:inst2|Mux6~743 control_unit:inst2|address[1] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.561 ns" { alu:inst|temp[12] {} alu:inst|Equal0~84 {} alu:inst|Equal0~85 {} control_unit:inst2|Mux6~742 {} control_unit:inst2|Mux6~743 {} control_unit:inst2|address[1] {} } { 0.000ns 0.555ns 0.532ns 0.545ns 0.580ns 0.202ns } { 0.000ns 0.366ns 0.053ns 0.053ns 0.366ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.009 ns - Smallest " "Info: - Smallest clock skew is 0.009 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.490 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 392 416 584 408 "clk" "" } { 272 640 736 288 "clk" "" } { 256 328 416 272 "clk" "" } { 32 -56 24 48 "clk" "" } { 32 328 416 48 "clk" "" } { 144 -56 24 160 "clk" "" } { 160 328 416 176 "clk" "" } { 272 -56 24 288 "clk" "" } { 400 -64 24 416 "clk" "" } { 528 -64 24 544 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 209 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 209; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 392 416 584 408 "clk" "" } { 272 640 736 288 "clk" "" } { 256 328 416 272 "clk" "" } { 32 -56 24 48 "clk" "" } { 32 328 416 48 "clk" "" } { 144 -56 24 160 "clk" "" } { 160 328 416 176 "clk" "" } { 272 -56 24 288 "clk" "" } { 400 -64 24 416 "clk" "" } { 528 -64 24 544 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.618 ns) 2.490 ns control_unit:inst2\|address\[1\] 3 REG LCFF_X7_Y23_N3 3 " "Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X7_Y23_N3; Fanout = 3; REG Node = 'control_unit:inst2\|address\[1\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.293 ns" { clk~clkctrl control_unit:inst2|address[1] } "NODE_NAME" } } { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.12 % ) " "Info: Total cell delay = 1.472 ns ( 59.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 40.88 % ) " "Info: Total interconnect delay = 1.018 ns ( 40.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl control_unit:inst2|address[1] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} control_unit:inst2|address[1] {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.481 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.481 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 392 416 584 408 "clk" "" } { 272 640 736 288 "clk" "" } { 256 328 416 272 "clk" "" } { 32 -56 24 48 "clk" "" } { 32 328 416 48 "clk" "" } { 144 -56 24 160 "clk" "" } { 160 328 416 176 "clk" "" } { 272 -56 24 288 "clk" "" } { 400 -64 24 416 "clk" "" } { 528 -64 24 544 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 209 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 209; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 392 416 584 408 "clk" "" } { 272 640 736 288 "clk" "" } { 256 328 416 272 "clk" "" } { 32 -56 24 48 "clk" "" } { 32 328 416 48 "clk" "" } { 144 -56 24 160 "clk" "" } { 160 328 416 176 "clk" "" } { 272 -56 24 288 "clk" "" } { 400 -64 24 416 "clk" "" } { 528 -64 24 544 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.666 ns) + CELL(0.618 ns) 2.481 ns alu:inst\|temp\[12\] 3 REG LCFF_X7_Y21_N15 5 " "Info: 3: + IC(0.666 ns) + CELL(0.618 ns) = 2.481 ns; Loc. = LCFF_X7_Y21_N15; Fanout = 5; REG Node = 'alu:inst\|temp\[12\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.284 ns" { clk~clkctrl alu:inst|temp[12] } "NODE_NAME" } } { "alu.vhd" "" { Text "F:/another way/cpu/alu.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.33 % ) " "Info: Total cell delay = 1.472 ns ( 59.33 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.009 ns ( 40.67 % ) " "Info: Total interconnect delay = 1.009 ns ( 40.67 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { clk clk~clkctrl alu:inst|temp[12] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.481 ns" { clk {} clk~combout {} clk~clkctrl {} alu:inst|temp[12] {} } { 0.000ns 0.000ns 0.343ns 0.666ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl control_unit:inst2|address[1] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} control_unit:inst2|address[1] {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { clk clk~clkctrl alu:inst|temp[12] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.481 ns" { clk {} clk~combout {} clk~clkctrl {} alu:inst|temp[12] {} } { 0.000ns 0.000ns 0.343ns 0.666ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "alu.vhd" "" { Text "F:/another way/cpu/alu.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.561 ns" { alu:inst|temp[12] alu:inst|Equal0~84 alu:inst|Equal0~85 control_unit:inst2|Mux6~742 control_unit:inst2|Mux6~743 control_unit:inst2|address[1] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.561 ns" { alu:inst|temp[12] {} alu:inst|Equal0~84 {} alu:inst|Equal0~85 {} control_unit:inst2|Mux6~742 {} control_unit:inst2|Mux6~743 {} control_unit:inst2|address[1] {} } { 0.000ns 0.555ns 0.532ns 0.545ns 0.580ns 0.202ns } { 0.000ns 0.366ns 0.053ns 0.053ns 0.366ns 0.309ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl control_unit:inst2|address[1] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} control_unit:inst2|address[1] {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.481 ns" { clk clk~clkctrl alu:inst|temp[12] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.481 ns" { clk {} clk~combout {} clk~clkctrl {} alu:inst|temp[12] {} } { 0.000ns 0.000ns 0.343ns 0.666ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk control_out\[4\] control_unit:inst2\|address_out\[4\] 7.463 ns register " "Info: tco from clock \"clk\" to destination pin \"control_out\[4\]\" through register \"control_unit:inst2\|address_out\[4\]\" is 7.463 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.490 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 2.490 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 392 416 584 408 "clk" "" } { 272 640 736 288 "clk" "" } { 256 328 416 272 "clk" "" } { 32 -56 24 48 "clk" "" } { 32 328 416 48 "clk" "" } { 144 -56 24 160 "clk" "" } { 160 328 416 176 "clk" "" } { 272 -56 24 288 "clk" "" } { 400 -64 24 416 "clk" "" } { 528 -64 24 544 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 209 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 209; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 392 416 584 408 "clk" "" } { 272 640 736 288 "clk" "" } { 256 328 416 272 "clk" "" } { 32 -56 24 48 "clk" "" } { 32 328 416 48 "clk" "" } { 144 -56 24 160 "clk" "" } { 160 328 416 176 "clk" "" } { 272 -56 24 288 "clk" "" } { 400 -64 24 416 "clk" "" } { 528 -64 24 544 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.675 ns) + CELL(0.618 ns) 2.490 ns control_unit:inst2\|address_out\[4\] 3 REG LCFF_X7_Y23_N29 3 " "Info: 3: + IC(0.675 ns) + CELL(0.618 ns) = 2.490 ns; Loc. = LCFF_X7_Y23_N29; Fanout = 3; REG Node = 'control_unit:inst2\|address_out\[4\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.293 ns" { clk~clkctrl control_unit:inst2|address_out[4] } "NODE_NAME" } } { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.12 % ) " "Info: Total cell delay = 1.472 ns ( 59.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.018 ns ( 40.88 % ) " "Info: Total interconnect delay = 1.018 ns ( 40.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl control_unit:inst2|address_out[4] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} control_unit:inst2|address_out[4] {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.879 ns + Longest register pin " "Info: + Longest register to pin delay is 4.879 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns control_unit:inst2\|address_out\[4\] 1 REG LCFF_X7_Y23_N29 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X7_Y23_N29; Fanout = 3; REG Node = 'control_unit:inst2\|address_out\[4\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { control_unit:inst2|address_out[4] } "NODE_NAME" } } { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.725 ns) + CELL(2.154 ns) 4.879 ns control_out\[4\] 2 PIN PIN_F2 0 " "Info: 2: + IC(2.725 ns) + CELL(2.154 ns) = 4.879 ns; Loc. = PIN_F2; Fanout = 0; PIN Node = 'control_out\[4\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.879 ns" { control_unit:inst2|address_out[4] control_out[4] } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 488 416 592 504 "control_out\[7..0\]" "" } { 256 608 736 272 "control_out\[7..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.154 ns ( 44.15 % ) " "Info: Total cell delay = 2.154 ns ( 44.15 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.725 ns ( 55.85 % ) " "Info: Total interconnect delay = 2.725 ns ( 55.85 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.879 ns" { control_unit:inst2|address_out[4] control_out[4] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "4.879 ns" { control_unit:inst2|address_out[4] {} control_out[4] {} } { 0.000ns 2.725ns } { 0.000ns 2.154ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.490 ns" { clk clk~clkctrl control_unit:inst2|address_out[4] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.490 ns" { clk {} clk~combout {} clk~clkctrl {} control_unit:inst2|address_out[4] {} } { 0.000ns 0.000ns 0.343ns 0.675ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.879 ns" { control_unit:inst2|address_out[4] control_out[4] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "4.879 ns" { control_unit:inst2|address_out[4] {} control_out[4] {} } { 0.000ns 2.725ns } { 0.000ns 2.154ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "119 " "Info: Allocated 119 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 29 14:19:36 2009 " "Info: Processing ended: Sun Mar 29 14:19:36 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}