cpu.tan.qmsg

用VHDL语言设计简单的CPU

{ "Info" "ITDB_FULL_TCO_RESULT" "clock memory\[5\] lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|q_a\[5\] 7.231 ns memory " "Info: tco from clock \"clock\" to destination pin \"memory\[5\]\" through memory \"lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|q_a\[5\]\" is 7.231 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.352 ns + Longest memory " "Info: + Longest clock path from clock \"clock\" to source memory is 2.352 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns clock 1 CLK PIN_M21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 376 416 584 392 "clock" "" } { 528 -64 24 544 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.207 ns clock~clkctrl 2 COMB CLKCTRL_G1 57 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 57; COMB Node = 'clock~clkctrl'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 376 416 584 392 "clock" "" } { 528 -64 24 544 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.673 ns) + CELL(0.472 ns) 2.352 ns lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|q_a\[5\] 3 MEM M4K_X8_Y22 2 " "Info: 3: + IC(0.673 ns) + CELL(0.472 ns) = 2.352 ns; Loc. = M4K_X8_Y22; Fanout = 2; MEM Node = 'lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|q_a\[5\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.145 ns" { clock~clkctrl lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[5] } "NODE_NAME" } } { "db/altsyncram_3ac1.tdf" "" { Text "F:/another way/cpu/db/altsyncram_3ac1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.336 ns ( 56.80 % ) " "Info: Total cell delay = 1.336 ns ( 56.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.016 ns ( 43.20 % ) " "Info: Total interconnect delay = 1.016 ns ( 43.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { clock clock~clkctrl lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[5] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[5] {} } { 0.000ns 0.000ns 0.343ns 0.673ns } { 0.000ns 0.864ns 0.000ns 0.472ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.136 ns + " "Info: + Micro clock to output delay of source is 0.136 ns" {  } { { "db/altsyncram_3ac1.tdf" "" { Text "F:/another way/cpu/db/altsyncram_3ac1.tdf" 32 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.743 ns + Longest memory pin " "Info: + Longest memory to pin delay is 4.743 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.051 ns) 0.051 ns lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|q_a\[5\] 1 MEM M4K_X8_Y22 2 " "Info: 1: + IC(0.000 ns) + CELL(0.051 ns) = 0.051 ns; Loc. = M4K_X8_Y22; Fanout = 2; MEM Node = 'lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|q_a\[5\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[5] } "NODE_NAME" } } { "db/altsyncram_3ac1.tdf" "" { Text "F:/another way/cpu/db/altsyncram_3ac1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.568 ns) + CELL(2.124 ns) 4.743 ns memory\[5\] 2 PIN PIN_J5 0 " "Info: 2: + IC(2.568 ns) + CELL(2.124 ns) = 4.743 ns; Loc. = PIN_J5; Fanout = 0; PIN Node = 'memory\[5\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.692 ns" { lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[5] memory[5] } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 520 416 592 536 "memory\[15..0\]" "" } { 240 -56 25 256 "memory\[15..0\]" "" } { 480 184 272 496 "memory\[15..0\]" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.175 ns ( 45.86 % ) " "Info: Total cell delay = 2.175 ns ( 45.86 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.568 ns ( 54.14 % ) " "Info: Total interconnect delay = 2.568 ns ( 54.14 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.743 ns" { lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[5] memory[5] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "4.743 ns" { lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[5] {} memory[5] {} } { 0.000ns 2.568ns } { 0.051ns 2.124ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { clock clock~clkctrl lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[5] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[5] {} } { 0.000ns 0.000ns 0.343ns 0.673ns } { 0.000ns 0.864ns 0.000ns 0.472ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "4.743 ns" { lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[5] memory[5] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "4.743 ns" { lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[5] {} memory[5] {} } { 0.000ns 2.568ns } { 0.051ns 2.124ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1  Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "119 " "Info: Allocated 119 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sun Mar 29 14:56:43 2009 " "Info: Processing ended: Sun Mar 29 14:56:43 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}