cpu.tan.qmsg

用VHDL语言设计简单的CPU

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 392 416 584 408 "clk" "" } { 272 640 736 288 "clk" "" } { 256 328 416 272 "clk" "" } { 32 -56 24 48 "clk" "" } { 32 328 416 48 "clk" "" } { 144 -56 24 160 "clk" "" } { 160 328 416 176 "clk" "" } { 272 -56 24 288 "clk" "" } { 400 -64 24 416 "clk" "" } } } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "clock " "Info: Assuming node \"clock\" is an undefined clock" {  } { { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 376 416 584 392 "clock" "" } { 528 -64 24 544 "clock" "" } } } } { "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/program files/quartus ii 7.2/quartus/bin/Assignment Editor.qase" 1 { { 0 "clock" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register alu:inst\|temp\[12\] register control_unit:inst2\|address\[2\] 310.46 MHz 3.221 ns Internal " "Info: Clock \"clk\" has Internal fmax of 310.46 MHz between source register \"alu:inst\|temp\[12\]\" and destination register \"control_unit:inst2\|address\[2\]\" (period= 3.221 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.025 ns + Longest register register " "Info: + Longest register to register delay is 3.025 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns alu:inst\|temp\[12\] 1 REG LCFF_X22_Y22_N19 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X22_Y22_N19; Fanout = 5; REG Node = 'alu:inst\|temp\[12\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { alu:inst|temp[12] } "NODE_NAME" } } { "alu.vhd" "" { Text "F:/another way/cpu/alu.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.600 ns) + CELL(0.366 ns) 0.966 ns alu:inst\|Equal0~84 2 COMB LCCOMB_X21_Y22_N18 1 " "Info: 2: + IC(0.600 ns) + CELL(0.366 ns) = 0.966 ns; Loc. = LCCOMB_X21_Y22_N18; Fanout = 1; COMB Node = 'alu:inst\|Equal0~84'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.966 ns" { alu:inst|temp[12] alu:inst|Equal0~84 } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.542 ns) + CELL(0.053 ns) 1.561 ns alu:inst\|Equal0~85 3 COMB LCCOMB_X21_Y23_N6 2 " "Info: 3: + IC(0.542 ns) + CELL(0.053 ns) = 1.561 ns; Loc. = LCCOMB_X21_Y23_N6; Fanout = 2; COMB Node = 'alu:inst\|Equal0~85'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.595 ns" { alu:inst|Equal0~84 alu:inst|Equal0~85 } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/program files/quartus ii 7.2/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.527 ns) + CELL(0.053 ns) 2.141 ns control_unit:inst2\|Mux5~1128 4 COMB LCCOMB_X19_Y23_N16 1 " "Info: 4: + IC(0.527 ns) + CELL(0.053 ns) = 2.141 ns; Loc. = LCCOMB_X19_Y23_N16; Fanout = 1; COMB Node = 'control_unit:inst2\|Mux5~1128'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.580 ns" { alu:inst|Equal0~85 control_unit:inst2|Mux5~1128 } "NODE_NAME" } } { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.310 ns) + CELL(0.053 ns) 2.504 ns control_unit:inst2\|Mux5~1129 5 COMB LCCOMB_X18_Y23_N8 2 " "Info: 5: + IC(0.310 ns) + CELL(0.053 ns) = 2.504 ns; Loc. = LCCOMB_X18_Y23_N8; Fanout = 2; COMB Node = 'control_unit:inst2\|Mux5~1129'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.363 ns" { control_unit:inst2|Mux5~1128 control_unit:inst2|Mux5~1129 } "NODE_NAME" } } { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 26 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.212 ns) + CELL(0.309 ns) 3.025 ns control_unit:inst2\|address\[2\] 6 REG LCFF_X18_Y23_N21 3 " "Info: 6: + IC(0.212 ns) + CELL(0.309 ns) = 3.025 ns; Loc. = LCFF_X18_Y23_N21; Fanout = 3; REG Node = 'control_unit:inst2\|address\[2\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.521 ns" { control_unit:inst2|Mux5~1129 control_unit:inst2|address[2] } "NODE_NAME" } } { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.834 ns ( 27.57 % ) " "Info: Total cell delay = 0.834 ns ( 27.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.191 ns ( 72.43 % ) " "Info: Total interconnect delay = 2.191 ns ( 72.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.025 ns" { alu:inst|temp[12] alu:inst|Equal0~84 alu:inst|Equal0~85 control_unit:inst2|Mux5~1128 control_unit:inst2|Mux5~1129 control_unit:inst2|address[2] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.025 ns" { alu:inst|temp[12] {} alu:inst|Equal0~84 {} alu:inst|Equal0~85 {} control_unit:inst2|Mux5~1128 {} control_unit:inst2|Mux5~1129 {} control_unit:inst2|address[2] {} } { 0.000ns 0.600ns 0.542ns 0.527ns 0.310ns 0.212ns } { 0.000ns 0.366ns 0.053ns 0.053ns 0.053ns 0.309ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.012 ns - Smallest " "Info: - Smallest clock skew is -0.012 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 2.471 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 2.471 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 392 416 584 408 "clk" "" } { 272 640 736 288 "clk" "" } { 256 328 416 272 "clk" "" } { 32 -56 24 48 "clk" "" } { 32 328 416 48 "clk" "" } { 144 -56 24 160 "clk" "" } { 160 328 416 176 "clk" "" } { 272 -56 24 288 "clk" "" } { 400 -64 24 416 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 152 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 152; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 392 416 584 408 "clk" "" } { 272 640 736 288 "clk" "" } { 256 328 416 272 "clk" "" } { 32 -56 24 48 "clk" "" } { 32 328 416 48 "clk" "" } { 144 -56 24 160 "clk" "" } { 160 328 416 176 "clk" "" } { 272 -56 24 288 "clk" "" } { 400 -64 24 416 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.656 ns) + CELL(0.618 ns) 2.471 ns control_unit:inst2\|address\[2\] 3 REG LCFF_X18_Y23_N21 3 " "Info: 3: + IC(0.656 ns) + CELL(0.618 ns) = 2.471 ns; Loc. = LCFF_X18_Y23_N21; Fanout = 3; REG Node = 'control_unit:inst2\|address\[2\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.274 ns" { clk~clkctrl control_unit:inst2|address[2] } "NODE_NAME" } } { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 20 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.57 % ) " "Info: Total cell delay = 1.472 ns ( 59.57 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.999 ns ( 40.43 % ) " "Info: Total interconnect delay = 0.999 ns ( 40.43 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.471 ns" { clk clk~clkctrl control_unit:inst2|address[2] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.471 ns" { clk {} clk~combout {} clk~clkctrl {} control_unit:inst2|address[2] {} } { 0.000ns 0.000ns 0.343ns 0.656ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 2.483 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 2.483 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.854 ns) 0.854 ns clk 1 CLK PIN_N20 1 " "Info: 1: + IC(0.000 ns) + CELL(0.854 ns) = 0.854 ns; Loc. = PIN_N20; Fanout = 1; CLK Node = 'clk'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 392 416 584 408 "clk" "" } { 272 640 736 288 "clk" "" } { 256 328 416 272 "clk" "" } { 32 -56 24 48 "clk" "" } { 32 328 416 48 "clk" "" } { 144 -56 24 160 "clk" "" } { 160 328 416 176 "clk" "" } { 272 -56 24 288 "clk" "" } { 400 -64 24 416 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.197 ns clk~clkctrl 2 COMB CLKCTRL_G3 152 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.197 ns; Loc. = CLKCTRL_G3; Fanout = 152; COMB Node = 'clk~clkctrl'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clk clk~clkctrl } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 392 416 584 408 "clk" "" } { 272 640 736 288 "clk" "" } { 256 328 416 272 "clk" "" } { 32 -56 24 48 "clk" "" } { 32 328 416 48 "clk" "" } { 144 -56 24 160 "clk" "" } { 160 328 416 176 "clk" "" } { 272 -56 24 288 "clk" "" } { 400 -64 24 416 "clk" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.668 ns) + CELL(0.618 ns) 2.483 ns alu:inst\|temp\[12\] 3 REG LCFF_X22_Y22_N19 5 " "Info: 3: + IC(0.668 ns) + CELL(0.618 ns) = 2.483 ns; Loc. = LCFF_X22_Y22_N19; Fanout = 5; REG Node = 'alu:inst\|temp\[12\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.286 ns" { clk~clkctrl alu:inst|temp[12] } "NODE_NAME" } } { "alu.vhd" "" { Text "F:/another way/cpu/alu.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.472 ns ( 59.28 % ) " "Info: Total cell delay = 1.472 ns ( 59.28 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.011 ns ( 40.72 % ) " "Info: Total interconnect delay = 1.011 ns ( 40.72 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.483 ns" { clk clk~clkctrl alu:inst|temp[12] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.483 ns" { clk {} clk~combout {} clk~clkctrl {} alu:inst|temp[12] {} } { 0.000ns 0.000ns 0.343ns 0.668ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.471 ns" { clk clk~clkctrl control_unit:inst2|address[2] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.471 ns" { clk {} clk~combout {} clk~clkctrl {} control_unit:inst2|address[2] {} } { 0.000ns 0.000ns 0.343ns 0.656ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.483 ns" { clk clk~clkctrl alu:inst|temp[12] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.483 ns" { clk {} clk~combout {} clk~clkctrl {} alu:inst|temp[12] {} } { 0.000ns 0.000ns 0.343ns 0.668ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.094 ns + " "Info: + Micro clock to output delay of source is 0.094 ns" {  } { { "alu.vhd" "" { Text "F:/another way/cpu/alu.vhd" 21 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.090 ns + " "Info: + Micro setup delay of destination is 0.090 ns" {  } { { "control_unit.vhd" "" { Text "F:/another way/cpu/control_unit.vhd" 20 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "3.025 ns" { alu:inst|temp[12] alu:inst|Equal0~84 alu:inst|Equal0~85 control_unit:inst2|Mux5~1128 control_unit:inst2|Mux5~1129 control_unit:inst2|address[2] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "3.025 ns" { alu:inst|temp[12] {} alu:inst|Equal0~84 {} alu:inst|Equal0~85 {} control_unit:inst2|Mux5~1128 {} control_unit:inst2|Mux5~1129 {} control_unit:inst2|address[2] {} } { 0.000ns 0.600ns 0.542ns 0.527ns 0.310ns 0.212ns } { 0.000ns 0.366ns 0.053ns 0.053ns 0.053ns 0.309ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.471 ns" { clk clk~clkctrl control_unit:inst2|address[2] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.471 ns" { clk {} clk~combout {} clk~clkctrl {} control_unit:inst2|address[2] {} } { 0.000ns 0.000ns 0.343ns 0.656ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.483 ns" { clk clk~clkctrl alu:inst|temp[12] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.483 ns" { clk {} clk~combout {} clk~clkctrl {} alu:inst|temp[12] {} } { 0.000ns 0.000ns 0.343ns 0.668ns } { 0.000ns 0.854ns 0.000ns 0.618ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT_RESTRICTED" "clock memory memory lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|ram_block1a0~porta_we_reg lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|q_a\[0\] 500.0 MHz Internal " "Info: Clock \"clock\" Internal fmax is restricted to 500.0 MHz between source memory \"lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|ram_block1a0~porta_we_reg\" and destination memory \"lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|q_a\[0\]\"" { { "Info" "ITDB_CLOCK_RATE" "clock 2.0 ns " "Info: fmax restricted to clock pin edge rate 2.0 ns. Expand message to see actual delay path." { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "1.623 ns + Longest memory memory " "Info: + Longest memory to memory delay is 1.623 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|ram_block1a0~porta_we_reg 1 MEM M4K_X8_Y22 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = M4K_X8_Y22; Fanout = 16; MEM Node = 'lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_3ac1.tdf" "" { Text "F:/another way/cpu/db/altsyncram_3ac1.tdf" 36 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.623 ns) 1.623 ns lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|q_a\[0\] 2 MEM M4K_X8_Y22 2 " "Info: 2: + IC(0.000 ns) + CELL(1.623 ns) = 1.623 ns; Loc. = M4K_X8_Y22; Fanout = 2; MEM Node = 'lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|q_a\[0\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.623 ns" { lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|ram_block1a0~porta_we_reg lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_3ac1.tdf" "" { Text "F:/another way/cpu/db/altsyncram_3ac1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.623 ns ( 100.00 % ) " "Info: Total cell delay = 1.623 ns ( 100.00 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.623 ns" { lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|ram_block1a0~porta_we_reg lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "1.623 ns" { lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|ram_block1a0~porta_we_reg {} lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[0] {} } { 0.000ns 0.000ns } { 0.000ns 1.623ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.009 ns - Smallest " "Info: - Smallest clock skew is -0.009 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock destination 2.352 ns + Shortest memory " "Info: + Shortest clock path from clock \"clock\" to destination memory is 2.352 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns clock 1 CLK PIN_M21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 376 416 584 392 "clock" "" } { 528 -64 24 544 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.207 ns clock~clkctrl 2 COMB CLKCTRL_G1 57 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 57; COMB Node = 'clock~clkctrl'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 376 416 584 392 "clock" "" } { 528 -64 24 544 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.673 ns) + CELL(0.472 ns) 2.352 ns lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|q_a\[0\] 3 MEM M4K_X8_Y22 2 " "Info: 3: + IC(0.673 ns) + CELL(0.472 ns) = 2.352 ns; Loc. = M4K_X8_Y22; Fanout = 2; MEM Node = 'lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|q_a\[0\]'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.145 ns" { clock~clkctrl lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[0] } "NODE_NAME" } } { "db/altsyncram_3ac1.tdf" "" { Text "F:/another way/cpu/db/altsyncram_3ac1.tdf" 32 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.336 ns ( 56.80 % ) " "Info: Total cell delay = 1.336 ns ( 56.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.016 ns ( 43.20 % ) " "Info: Total interconnect delay = 1.016 ns ( 43.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { clock clock~clkctrl lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[0] {} } { 0.000ns 0.000ns 0.343ns 0.673ns } { 0.000ns 0.864ns 0.000ns 0.472ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clock source 2.361 ns - Longest memory " "Info: - Longest clock path from clock \"clock\" to source memory is 2.361 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.864 ns) 0.864 ns clock 1 CLK PIN_M21 1 " "Info: 1: + IC(0.000 ns) + CELL(0.864 ns) = 0.864 ns; Loc. = PIN_M21; Fanout = 1; CLK Node = 'clock'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { clock } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 376 416 584 392 "clock" "" } { 528 -64 24 544 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.343 ns) + CELL(0.000 ns) 1.207 ns clock~clkctrl 2 COMB CLKCTRL_G1 57 " "Info: 2: + IC(0.343 ns) + CELL(0.000 ns) = 1.207 ns; Loc. = CLKCTRL_G1; Fanout = 57; COMB Node = 'clock~clkctrl'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "0.343 ns" { clock clock~clkctrl } "NODE_NAME" } } { "cpu.bdf" "" { Schematic "F:/another way/cpu/cpu.bdf" { { 376 416 584 392 "clock" "" } { 528 -64 24 544 "clock" "" } } } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.673 ns) + CELL(0.481 ns) 2.361 ns lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|ram_block1a0~porta_we_reg 3 MEM M4K_X8_Y22 16 " "Info: 3: + IC(0.673 ns) + CELL(0.481 ns) = 2.361 ns; Loc. = M4K_X8_Y22; Fanout = 16; MEM Node = 'lpm_ram_dq0:inst7\|altsyncram:altsyncram_component\|altsyncram_3ac1:auto_generated\|ram_block1a0~porta_we_reg'" {  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.154 ns" { clock~clkctrl lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "db/altsyncram_3ac1.tdf" "" { Text "F:/another way/cpu/db/altsyncram_3ac1.tdf" 36 2 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.345 ns ( 56.97 % ) " "Info: Total cell delay = 1.345 ns ( 56.97 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.016 ns ( 43.03 % ) " "Info: Total interconnect delay = 1.016 ns ( 43.03 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.361 ns" { clock clock~clkctrl lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.361 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.343ns 0.673ns } { 0.000ns 0.864ns 0.000ns 0.481ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { clock clock~clkctrl lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[0] {} } { 0.000ns 0.000ns 0.343ns 0.673ns } { 0.000ns 0.864ns 0.000ns 0.472ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.361 ns" { clock clock~clkctrl lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.361 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.343ns 0.673ns } { 0.000ns 0.864ns 0.000ns 0.481ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.136 ns + " "Info: + Micro clock to output delay of source is 0.136 ns" {  } { { "db/altsyncram_3ac1.tdf" "" { Text "F:/another way/cpu/db/altsyncram_3ac1.tdf" 36 2 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.022 ns + " "Info: + Micro setup delay of destination is 0.022 ns" {  } { { "db/altsyncram_3ac1.tdf" "" { Text "F:/another way/cpu/db/altsyncram_3ac1.tdf" 32 2 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "1.623 ns" { lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|ram_block1a0~porta_we_reg lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "1.623 ns" { lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|ram_block1a0~porta_we_reg {} lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[0] {} } { 0.000ns 0.000ns } { 0.000ns 1.623ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.352 ns" { clock clock~clkctrl lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.352 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[0] {} } { 0.000ns 0.000ns 0.343ns 0.673ns } { 0.000ns 0.864ns 0.000ns 0.472ns } "" } } { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "2.361 ns" { clock clock~clkctrl lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|ram_block1a0~porta_we_reg } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "2.361 ns" { clock {} clock~combout {} clock~clkctrl {} lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|ram_block1a0~porta_we_reg {} } { 0.000ns 0.000ns 0.343ns 0.673ns } { 0.000ns 0.864ns 0.000ns 0.481ns } "" } }  } 0 0 "fmax restricted to %1!s! pin edge rate %2!s!. Expand message to see actual delay path." 0 0 "" 0}  } { { "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/quartus ii 7.2/quartus/bin/TimingClosureFloorplan.fld" "" "" { lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[0] } "NODE_NAME" } } { "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/quartus ii 7.2/quartus/bin/Technology_Viewer.qrui" "" { lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|q_a[0] {} } { 0.000ns } { 0.051ns } "" } } { "db/altsyncram_3ac1.tdf" "" { Text "F:/another way/cpu/db/altsyncram_3ac1.tdf" 32 2 0 } }  } 0 0 "Clock \"%1!s!\" %7!s! fmax is restricted to %6!s! between source %2!s! \"%4!s!\" and destination %3!s! \"%5!s!\"" 0 0 "" 0}