📄 cpu.vwf

📁 用VHDL语言设计简单的CPU
💻 VWF
📖 第 1 页 / 共 4 页
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	PARENT = "mbr";
}

SIGNAL("mbr[14]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "mbr";
}

SIGNAL("mbr[13]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "mbr";
}

SIGNAL("mbr[12]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "mbr";
}

SIGNAL("mbr[11]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "mbr";
}

SIGNAL("mbr[10]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "mbr";
}

SIGNAL("mbr[9]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "mbr";
}

SIGNAL("mbr[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "mbr";
}

SIGNAL("mbr[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "mbr";
}

SIGNAL("mbr[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "mbr";
}

SIGNAL("mbr[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "mbr";
}

SIGNAL("mbr[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "mbr";
}

SIGNAL("mbr[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "mbr";
}

SIGNAL("mbr[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "mbr";
}

SIGNAL("mbr[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "mbr";
}

SIGNAL("mbr[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "mbr";
}

SIGNAL("memory")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 16;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("memory[15]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("memory[14]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("memory[13]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("memory[12]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("memory[11]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("memory[10]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("memory[9]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("memory[8]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("memory[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("memory[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("memory[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("memory[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("memory[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("memory[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("memory[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("memory[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "memory";
}

SIGNAL("pc")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = BUS;
	WIDTH = 8;
	LSB_INDEX = 0;
	DIRECTION = OUTPUT;
	PARENT = "";
}

SIGNAL("pc[7]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "pc";
}

SIGNAL("pc[6]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "pc";
}

SIGNAL("pc[5]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "pc";
}

SIGNAL("pc[4]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "pc";
}

SIGNAL("pc[3]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "pc";
}

SIGNAL("pc[2]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "pc";
}

SIGNAL("pc[1]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "pc";
}

SIGNAL("pc[0]")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = OUTPUT;
	PARENT = "pc";
}

SIGNAL("clock")
{
	VALUE_TYPE = NINE_LEVEL_BIT;
	SIGNAL_TYPE = SINGLE_BIT;
	WIDTH = 1;
	LSB_INDEX = -1;
	DIRECTION = INPUT;
	PARENT = "";
}

TRANSITION_LIST("acc[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("acc[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("acc[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("acc[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("acc[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("acc[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("acc[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("acc[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("acc[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("acc[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("acc[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("acc[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("acc[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("acc[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("acc[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("acc[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[9]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[8]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("br[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("clk")
{
	NODE
	{
		REPEAT = 1;
		LEVEL 1 FOR 5.0;
		LEVEL 0 FOR 5.0;
		NODE
		{
			REPEAT = 59998;
			LEVEL 1 FOR 5.0;
			LEVEL 0 FOR 5.0;
		}
		LEVEL 1 FOR 5.0;
		LEVEL 0 FOR 5.0;
	}
}

TRANSITION_LIST("control_out[7]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("control_out[6]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("control_out[5]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("control_out[4]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("control_out[3]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("control_out[2]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("control_out[1]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("control_out[0]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[31]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[30]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[29]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[28]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[27]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[26]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[25]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[24]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[23]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[22]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[21]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[20]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[19]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[18]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[17]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[16]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[15]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[14]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[13]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[12]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[11]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[10]")
{
	NODE
	{
		REPEAT = 1;
		LEVEL X FOR 600000.0;
	}
}

TRANSITION_LIST("cs[9]")
{
💿 文件大小 1240 K
👤 上传用户 cjf0426
📂 所属分类 VHDL/FPGA/Verilog
🏷️ 相关标签

#VHDL #CPU #语言
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