cpu.map.rpt

用VHDL语言设计简单的CPU

; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                            ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                            ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                            ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                            ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                            ;
; WIDTH_B                            ; 1                    ; Untyped                            ;
; WIDTHAD_B                          ; 1                    ; Untyped                            ;
; NUMWORDS_B                         ; 1                    ; Untyped                            ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                            ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                            ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                            ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                            ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                            ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                            ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                            ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                            ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                            ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                            ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                            ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                            ;
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer                     ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                            ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                            ;
; BYTE_SIZE                          ; 8                    ; Untyped                            ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                            ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                            ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                            ;
; INIT_FILE                          ; memory.mif           ; Untyped                            ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                            ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                            ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                            ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                            ;
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS               ; Untyped                            ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                            ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                            ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                            ;
; ENABLE_ECC                         ; FALSE                ; Untyped                            ;
; DEVICE_FAMILY                      ; Stratix II           ; Untyped                            ;
; CBXI_PARAMETER                     ; altsyncram_3ac1      ; Untyped                            ;
+------------------------------------+----------------------+------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Sun Mar 29 14:56:14 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpu -c cpu
Info: Found 2 design units, including 1 entities, in source file br.vhd
    Info: Found design unit 1: br-behave
    Info: Found entity 1: br
Info: Found 2 design units, including 1 entities, in source file alu.vhd
    Info: Found design unit 1: alu-behave
    Info: Found entity 1: alu
Info: Found 2 design units, including 1 entities, in source file mbr.vhd
    Info: Found design unit 1: mbr-behave
    Info: Found entity 1: mbr
Info: Found 2 design units, including 1 entities, in source file ir.vhd
    Info: Found design unit 1: ir-behave
    Info: Found entity 1: ir
Info: Found 2 design units, including 1 entities, in source file pc.vhd
    Info: Found design unit 1: pc-behave
    Info: Found entity 1: pc
Info: Found 2 design units, including 1 entities, in source file mar.vhd
    Info: Found design unit 1: mar-behave
    Info: Found entity 1: mar
Info: Found 2 design units, including 1 entities, in source file control_unit.vhd
    Info: Found design unit 1: control_unit-behave
    Info: Found entity 1: control_unit
Info: Found 1 design units, including 1 entities, in source file cpu.bdf
    Info: Found entity 1: cpu
Info: Elaborating entity "cpu" for the top level hierarchy
Info: Elaborating entity "alu" for hierarchy "alu:inst"
Info: Elaborating entity "br" for hierarchy "br:inst1"
Warning: Using design file lpm_rom0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_rom0-SYN
    Info: Found entity 1: lpm_rom0
Info: Elaborating entity "lpm_rom0" for hierarchy "lpm_rom0:inst8"
Info: Found 1 design units, including 1 entities, in source file d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/altsyncram.tdf
    Info: Found entity 1: altsyncram
Info: Elaborating entity "altsyncram" for hierarchy "lpm_rom0:inst8|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "lpm_rom0:inst8|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_js61.tdf
    Info: Found entity 1: altsyncram_js61
Info: Elaborating entity "altsyncram_js61" for hierarchy "lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated"
Info: Elaborating entity "control_unit" for hierarchy "control_unit:inst2"
Info: Elaborating entity "ir" for hierarchy "ir:inst4"
Info: Elaborating entity "mbr" for hierarchy "mbr:inst3"
Warning: Using design file lpm_ram_dq0.vhd, which is not specified as a design file for the current project, but contains definitions for 2 design units and 1 entities in project
    Info: Found design unit 1: lpm_ram_dq0-SYN
    Info: Found entity 1: lpm_ram_dq0
Info: Elaborating entity "lpm_ram_dq0" for hierarchy "lpm_ram_dq0:inst7"
Info: Elaborating entity "altsyncram" for hierarchy "lpm_ram_dq0:inst7|altsyncram:altsyncram_component"
Info: Elaborated megafunction instantiation "lpm_ram_dq0:inst7|altsyncram:altsyncram_component"
Info: Found 1 design units, including 1 entities, in source file db/altsyncram_3ac1.tdf
    Info: Found entity 1: altsyncram_3ac1
Info: Elaborating entity "altsyncram_3ac1" for hierarchy "lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated"
Info: Elaborating entity "mar" for hierarchy "mar:inst6"
Info: Elaborating entity "pc" for hierarchy "pc:inst5"
Info: Duplicate registers merged to single register
    Info: Duplicate register "pc:inst5|pc_out[2]" merged to single register "pc:inst5|temp[2]"
    Info: Duplicate register "pc:inst5|pc_out[1]" merged to single register "pc:inst5|temp[1]"
    Info: Duplicate register "pc:inst5|pc_out[0]" merged to single register "pc:inst5|temp[0]"
    Info: Duplicate register "pc:inst5|temp[7]" merged to single register "pc:inst5|pc_out[7]"
    Info: Duplicate register "pc:inst5|temp[6]" merged to single register "pc:inst5|pc_out[6]"
    Info: Duplicate register "pc:inst5|temp[5]" merged to single register "pc:inst5|pc_out[5]"
    Info: Duplicate register "pc:inst5|temp[4]" merged to single register "pc:inst5|pc_out[4]"
    Info: Duplicate register "pc:inst5|temp[3]" merged to single register "pc:inst5|pc_out[3]"
Info: Implemented 340 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 128 output pins
    Info: Implemented 162 logic cells
    Info: Implemented 48 RAM segments
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
    Info: Allocated 172 megabytes of memory during processing
    Info: Processing ended: Sun Mar 29 14:56:22 2009
    Info: Elapsed time: 00:00:08