cpu.map.rpt

用VHDL语言设计简单的CPU

+---------------------------------------+--------------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 104   ;
; Number of registers using Synchronous Clear  ; 30    ;
; Number of registers using Synchronous Load   ; 40    ;
; Number of registers using Asynchronous Clear ; 0     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 78    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                   ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output         ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+
; 3:1                ; 8 bits    ; 16 ALUTs      ; 0 ALUTs              ; 16 ALUTs               ; Yes        ; |cpu|pc:inst5|pc_out[5]            ;
; 3:1                ; 16 bits   ; 32 ALUTs      ; 0 ALUTs              ; 32 ALUTs               ; Yes        ; |cpu|mbr:inst3|mbr_out[15]         ;
; 3:1                ; 8 bits    ; 16 ALUTs      ; 0 ALUTs              ; 16 ALUTs               ; Yes        ; |cpu|mar:inst6|mar_out[6]          ;
; 4:1                ; 8 bits    ; 16 ALUTs      ; 0 ALUTs              ; 16 ALUTs               ; Yes        ; |cpu|control_unit:inst2|address[3] ;
; 9:1                ; 14 bits   ; 84 ALUTs      ; 56 ALUTs             ; 28 ALUTs               ; Yes        ; |cpu|alu:inst|temp[12]             ;
; 256:1              ; 6 bits    ; 1020 ALUTs    ; 48 ALUTs             ; 972 ALUTs              ; No         ; |cpu|control_unit:inst2|Mux0       ;
; 256:1              ; 2 bits    ; 340 ALUTs     ; 14 ALUTs             ; 326 ALUTs              ; No         ; |cpu|control_unit:inst2|Mux5       ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+------------------------------------+


+------------------------------------------------------------------------------------------------------+
; Source assignments for lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated ;
+---------------------------------+--------------------+------+----------------------------------------+
; Assignment                      ; Value              ; From ; To                                     ;
+---------------------------------+--------------------+------+----------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                      ;
+---------------------------------+--------------------+------+----------------------------------------+


+---------------------------------------------------------------------------------------------------------+
; Source assignments for lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated ;
+---------------------------------+--------------------+------+-------------------------------------------+
; Assignment                      ; Value              ; From ; To                                        ;
+---------------------------------+--------------------+------+-------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                         ;
+---------------------------------+--------------------+------+-------------------------------------------+


+---------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_rom0:inst8|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+---------------------------------+
; Parameter Name                     ; Value                ; Type                            ;
+------------------------------------+----------------------+---------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                         ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                      ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                    ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                    ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                  ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                         ;
; OPERATION_MODE                     ; ROM                  ; Untyped                         ;
; WIDTH_A                            ; 32                   ; Signed Integer                  ;
; WIDTHAD_A                          ; 8                    ; Signed Integer                  ;
; NUMWORDS_A                         ; 256                  ; Signed Integer                  ;
; OUTDATA_REG_A                      ; CLOCK0               ; Untyped                         ;
; ADDRESS_ACLR_A                     ; NONE                 ; Untyped                         ;
; OUTDATA_ACLR_A                     ; NONE                 ; Untyped                         ;
; WRCONTROL_ACLR_A                   ; NONE                 ; Untyped                         ;
; INDATA_ACLR_A                      ; NONE                 ; Untyped                         ;
; BYTEENA_ACLR_A                     ; NONE                 ; Untyped                         ;
; WIDTH_B                            ; 1                    ; Untyped                         ;
; WIDTHAD_B                          ; 1                    ; Untyped                         ;
; NUMWORDS_B                         ; 1                    ; Untyped                         ;
; INDATA_REG_B                       ; CLOCK1               ; Untyped                         ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1               ; Untyped                         ;
; RDCONTROL_REG_B                    ; CLOCK1               ; Untyped                         ;
; ADDRESS_REG_B                      ; CLOCK1               ; Untyped                         ;
; OUTDATA_REG_B                      ; UNREGISTERED         ; Untyped                         ;
; BYTEENA_REG_B                      ; CLOCK1               ; Untyped                         ;
; INDATA_ACLR_B                      ; NONE                 ; Untyped                         ;
; WRCONTROL_ACLR_B                   ; NONE                 ; Untyped                         ;
; ADDRESS_ACLR_B                     ; NONE                 ; Untyped                         ;
; OUTDATA_ACLR_B                     ; NONE                 ; Untyped                         ;
; RDCONTROL_ACLR_B                   ; NONE                 ; Untyped                         ;
; BYTEENA_ACLR_B                     ; NONE                 ; Untyped                         ;
; WIDTH_BYTEENA_A                    ; 1                    ; Signed Integer                  ;
; WIDTH_BYTEENA_B                    ; 1                    ; Untyped                         ;
; RAM_BLOCK_TYPE                     ; AUTO                 ; Untyped                         ;
; BYTE_SIZE                          ; 8                    ; Untyped                         ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE            ; Untyped                         ;
; READ_DURING_WRITE_MODE_PORT_A      ; NEW_DATA_NO_NBE_READ ; Untyped                         ;
; READ_DURING_WRITE_MODE_PORT_B      ; NEW_DATA_NO_NBE_READ ; Untyped                         ;
; INIT_FILE                          ; rom.mif              ; Untyped                         ;
; INIT_FILE_LAYOUT                   ; PORT_A               ; Untyped                         ;
; MAXIMUM_DEPTH                      ; 0                    ; Untyped                         ;
; CLOCK_ENABLE_INPUT_A               ; BYPASS               ; Untyped                         ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL               ; Untyped                         ;
; CLOCK_ENABLE_OUTPUT_A              ; BYPASS               ; Untyped                         ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL               ; Untyped                         ;
; CLOCK_ENABLE_CORE_A                ; USE_INPUT_CLKEN      ; Untyped                         ;
; CLOCK_ENABLE_CORE_B                ; USE_INPUT_CLKEN      ; Untyped                         ;
; ENABLE_ECC                         ; FALSE                ; Untyped                         ;
; DEVICE_FAMILY                      ; Stratix II           ; Untyped                         ;
; CBXI_PARAMETER                     ; altsyncram_js61      ; Untyped                         ;
+------------------------------------+----------------------+---------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+------------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: lpm_ram_dq0:inst7|altsyncram:altsyncram_component ;
+------------------------------------+----------------------+------------------------------------+
; Parameter Name                     ; Value                ; Type                               ;
+------------------------------------+----------------------+------------------------------------+
; BYTE_SIZE_BLOCK                    ; 8                    ; Untyped                            ;
; AUTO_CARRY_CHAINS                  ; ON                   ; AUTO_CARRY                         ;
; IGNORE_CARRY_BUFFERS               ; OFF                  ; IGNORE_CARRY                       ;
; AUTO_CASCADE_CHAINS                ; ON                   ; AUTO_CASCADE                       ;
; IGNORE_CASCADE_BUFFERS             ; OFF                  ; IGNORE_CASCADE                     ;
; WIDTH_BYTEENA                      ; 1                    ; Untyped                            ;
; OPERATION_MODE                     ; SINGLE_PORT          ; Untyped                            ;
; WIDTH_A                            ; 16                   ; Signed Integer                     ;
; WIDTHAD_A                          ; 8                    ; Signed Integer                     ;
; NUMWORDS_A                         ; 256                  ; Signed Integer                     ;
; OUTDATA_REG_A                      ; CLOCK0               ; Untyped                            ;