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📄 cpu.map.rpt

📁 用VHDL语言设计简单的CPU
💻 RPT
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; HDL message level                                                           ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                             ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                    ; 100                ; 100                ;
; Clock MUX Protection                                                        ; On                 ; On                 ;
; Block Design Naming                                                         ; Auto               ; Auto               ;
+-----------------------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                                                          ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type                          ; File Name with Absolute Path                                                          ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------+
; br.vhd                           ; yes             ; User VHDL File                     ; F:/another way/cpu/br.vhd                                                             ;
; alu.vhd                          ; yes             ; User VHDL File                     ; F:/another way/cpu/alu.vhd                                                            ;
; mbr.vhd                          ; yes             ; User VHDL File                     ; F:/another way/cpu/mbr.vhd                                                            ;
; ir.vhd                           ; yes             ; User VHDL File                     ; F:/another way/cpu/ir.vhd                                                             ;
; pc.vhd                           ; yes             ; User VHDL File                     ; F:/another way/cpu/pc.vhd                                                             ;
; mar.vhd                          ; yes             ; User VHDL File                     ; F:/another way/cpu/mar.vhd                                                            ;
; control_unit.vhd                 ; yes             ; User VHDL File                     ; F:/another way/cpu/control_unit.vhd                                                   ;
; cpu.bdf                          ; yes             ; User Block Diagram/Schematic File  ; F:/another way/cpu/cpu.bdf                                                            ;
; lpm_rom0.vhd                     ; yes             ; Other                              ; F:/another way/cpu/lpm_rom0.vhd                                                       ;
; altsyncram.tdf                   ; yes             ; Megafunction                       ; d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/altsyncram.tdf        ;
; stratix_ram_block.inc            ; yes             ; Megafunction                       ; d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/stratix_ram_block.inc ;
; lpm_mux.inc                      ; yes             ; Megafunction                       ; d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/lpm_mux.inc           ;
; lpm_decode.inc                   ; yes             ; Megafunction                       ; d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/lpm_decode.inc        ;
; aglobal72.inc                    ; yes             ; Megafunction                       ; d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/aglobal72.inc         ;
; a_rdenreg.inc                    ; yes             ; Megafunction                       ; d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/a_rdenreg.inc         ;
; altrom.inc                       ; yes             ; Megafunction                       ; d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/altrom.inc            ;
; altram.inc                       ; yes             ; Megafunction                       ; d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/altram.inc            ;
; altdpram.inc                     ; yes             ; Megafunction                       ; d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/altdpram.inc          ;
; altqpram.inc                     ; yes             ; Megafunction                       ; d:/program files/quartus ii 7.2/quartus/libraries/megafunctions/altqpram.inc          ;
; db/altsyncram_js61.tdf           ; yes             ; Auto-Generated Megafunction        ; F:/another way/cpu/db/altsyncram_js61.tdf                                             ;
; lpm_ram_dq0.vhd                  ; yes             ; Other                              ; F:/another way/cpu/lpm_ram_dq0.vhd                                                    ;
; db/altsyncram_3ac1.tdf           ; yes             ; Auto-Generated Megafunction        ; F:/another way/cpu/db/altsyncram_3ac1.tdf                                             ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------------------------------+


+-------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary           ;
+-----------------------------------------------+-------+
; Resource                                      ; Usage ;
+-----------------------------------------------+-------+
; Estimated ALUTs Used                          ; 90    ;
; Dedicated logic registers                     ; 104   ;
;                                               ;       ;
; Estimated ALUTs Unavailable                   ; 27    ;
;                                               ;       ;
; Total combinational functions                 ; 90    ;
; Combinational ALUT usage by number of inputs  ;       ;
;     -- 7 input functions                      ; 1     ;
;     -- 6 input functions                      ; 21    ;
;     -- 5 input functions                      ; 21    ;
;     -- 4 input functions                      ; 6     ;
;     -- <=3 input functions                    ; 41    ;
;                                               ;       ;
; Combinational ALUTs by mode                   ;       ;
;     -- normal mode                            ; 56    ;
;     -- extended LUT mode                      ; 1     ;
;     -- arithmetic mode                        ; 33    ;
;     -- shared arithmetic mode                 ; 0     ;
;                                               ;       ;
; Estimated ALUT/register pairs used            ; 117   ;
;                                               ;       ;
; Total registers                               ; 104   ;
;     -- Dedicated logic registers              ; 104   ;
;     -- I/O registers                          ; 0     ;
;                                               ;       ;
; Estimated ALMs:  partially or completely used ; 59    ;
;                                               ;       ;
; I/O pins                                      ; 130   ;
; Total block memory bits                       ; 12288 ;
; Maximum fan-out node                          ; clk   ;
; Maximum fan-out                               ; 136   ;
; Total fan-out                                 ; 1366  ;
; Average fan-out                               ; 3.67  ;
+-----------------------------------------------+-------+


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                                                                                                                            ;
+-------------------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------------------------------------------------------------------------+--------------+
; Compilation Hierarchy Node                ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name                                                                   ; Library Name ;
+-------------------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------------------------------------------------------------------------+--------------+
; |cpu                                      ; 90 (0)            ; 104 (0)      ; 12288             ; 0            ; 0       ; 0         ; 0         ; 130  ; 0            ; |cpu                                                                                  ; work         ;
;    |alu:inst|                             ; 57 (57)           ; 32 (32)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |cpu|alu:inst                                                                         ; work         ;
;    |br:inst1|                             ; 0 (0)             ; 16 (16)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |cpu|br:inst1                                                                         ; work         ;
;    |control_unit:inst2|                   ; 23 (23)           ; 16 (16)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |cpu|control_unit:inst2                                                               ; work         ;
;    |ir:inst4|                             ; 0 (0)             ; 8 (8)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |cpu|ir:inst4                                                                         ; work         ;
;    |lpm_ram_dq0:inst7|                    ; 0 (0)             ; 0 (0)        ; 4096              ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |cpu|lpm_ram_dq0:inst7                                                                ; work         ;
;       |altsyncram:altsyncram_component|   ; 0 (0)             ; 0 (0)        ; 4096              ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |cpu|lpm_ram_dq0:inst7|altsyncram:altsyncram_component                                ; work         ;
;          |altsyncram_3ac1:auto_generated| ; 0 (0)             ; 0 (0)        ; 4096              ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |cpu|lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated ; work         ;
;    |lpm_rom0:inst8|                       ; 0 (0)             ; 0 (0)        ; 8192              ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |cpu|lpm_rom0:inst8                                                                   ; work         ;
;       |altsyncram:altsyncram_component|   ; 0 (0)             ; 0 (0)        ; 8192              ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |cpu|lpm_rom0:inst8|altsyncram:altsyncram_component                                   ; work         ;
;          |altsyncram_js61:auto_generated| ; 0 (0)             ; 0 (0)        ; 8192              ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |cpu|lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated    ; work         ;
;    |mar:inst6|                            ; 1 (1)             ; 8 (8)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |cpu|mar:inst6                                                                        ; work         ;
;    |mbr:inst3|                            ; 1 (1)             ; 16 (16)      ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |cpu|mbr:inst3                                                                        ; work         ;
;    |pc:inst5|                             ; 8 (8)             ; 8 (8)        ; 0                 ; 0            ; 0       ; 0         ; 0         ; 0    ; 0            ; |cpu|pc:inst5                                                                         ; work         ;
+-------------------------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+---------------------------------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                 ;
+---------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+------------+
; Name                                                                                        ; Type ; Mode        ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size ; MIF        ;
+---------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+------------+
; lpm_ram_dq0:inst7|altsyncram:altsyncram_component|altsyncram_3ac1:auto_generated|ALTSYNCRAM ; AUTO ; Single Port ; 256          ; 16           ; --           ; --           ; 4096 ; memory.mif ;
; lpm_rom0:inst8|altsyncram:altsyncram_component|altsyncram_js61:auto_generated|ALTSYNCRAM    ; AUTO ; ROM         ; 256          ; 32           ; --           ; --           ; 8192 ; rom.mif    ;
+---------------------------------------------------------------------------------------------+------+-------------+--------------+--------------+--------------+--------------+------+------------+


+------------------------------------------------------------------------+
; Registers Removed During Synthesis                                     ;
+---------------------------------------+--------------------------------+
; Register name                         ; Reason for Removal             ;
+---------------------------------------+--------------------------------+
; pc:inst5|pc_out[2]                    ; Merged with pc:inst5|temp[2]   ;
; pc:inst5|pc_out[1]                    ; Merged with pc:inst5|temp[1]   ;
; pc:inst5|pc_out[0]                    ; Merged with pc:inst5|temp[0]   ;
; pc:inst5|temp[7]                      ; Merged with pc:inst5|pc_out[7] ;
; pc:inst5|temp[6]                      ; Merged with pc:inst5|pc_out[6] ;
; pc:inst5|temp[5]                      ; Merged with pc:inst5|pc_out[5] ;
; pc:inst5|temp[4]                      ; Merged with pc:inst5|pc_out[4] ;
; pc:inst5|temp[3]                      ; Merged with pc:inst5|pc_out[3] ;
; Total Number of Removed Registers = 8 ;                                ;

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