cpu.tan.rpt

用VHDL语言设计简单的CPU

+----------------------------------------------------------------+--------------------+------+----+-------------+
; Option                                                         ; Setting            ; From ; To ; Entity Name ;
+----------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name                                                    ; EP2S15F484C3       ;      ;    ;             ;
; Timing Models                                                  ; Final              ;      ;    ;             ;
; Default hold multicycle                                        ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains                      ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                         ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                                 ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                               ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                          ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements                        ; On                 ;      ;    ;             ;
; Enable Recovery/Removal analysis                               ; Off                ;      ;    ;             ;
; Enable Clock Latency                                           ; Off                ;      ;    ;             ;
; Use TimeQuest Timing Analyzer                                  ; Off                ;      ;    ;             ;
; Number of source nodes to report per destination node          ; 10                 ;      ;    ;             ;
; Number of destination nodes to report                          ; 10                 ;      ;    ;             ;
; Number of paths to report                                      ; 200                ;      ;    ;             ;
; Report Minimum Timing Checks                                   ; Off                ;      ;    ;             ;
; Use Fast Timing Models                                         ; Off                ;      ;    ;             ;
; Report IO Paths Separately                                     ; Off                ;      ;    ;             ;
; Perform Multicorner Analysis                                   ; On                 ;      ;    ;             ;
; Reports the worst-case path for each clock domain and analysis ; Off                ;      ;    ;             ;
+----------------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk             ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
; clock           ;                    ; User Pin ; None             ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk'                                                                                                                                                                                                                                                                                                                    ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                  ; To                                ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------+-----------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 310.46 MHz ( period = 3.221 ns )                    ; alu:inst|temp[12]                                                                     ; control_unit:inst2|address[2]     ; clk        ; clk      ; None                        ; None                      ; 3.025 ns                ;
; N/A                                     ; 311.24 MHz ( period = 3.213 ns )                    ; alu:inst|temp[12]                                                                     ; control_unit:inst2|address[1]     ; clk        ; clk      ; None                        ; None                      ; 3.017 ns                ;
; N/A                                     ; 326.58 MHz ( period = 3.062 ns )                    ; alu:inst|temp[3]                                                                      ; control_unit:inst2|address[2]     ; clk        ; clk      ; None                        ; None                      ; 2.863 ns                ;
; N/A                                     ; 327.44 MHz ( period = 3.054 ns )                    ; alu:inst|temp[3]                                                                      ; control_unit:inst2|address[1]     ; clk        ; clk      ; None                        ; None                      ; 2.855 ns                ;
; N/A                                     ; 335.68 MHz ( period = 2.979 ns )                    ; alu:inst|temp[1]                                                                      ; control_unit:inst2|address[2]     ; clk        ; clk      ; None                        ; None                      ; 2.778 ns                ;
; N/A                                     ; 336.59 MHz ( period = 2.971 ns )                    ; alu:inst|temp[1]                                                                      ; control_unit:inst2|address[1]     ; clk        ; clk      ; None                        ; None                      ; 2.770 ns                ;
; N/A                                     ; 336.81 MHz ( period = 2.969 ns )                    ; br:inst1|br_out[5]                                                                    ; alu:inst|temp[6]                  ; clk        ; clk      ; None                        ; None                      ; 2.784 ns                ;
; N/A                                     ; 337.50 MHz ( period = 2.963 ns )                    ; alu:inst|temp[13]                                                                     ; control_unit:inst2|address[2]     ; clk        ; clk      ; None                        ; None                      ; 2.767 ns                ;
; N/A                                     ; 338.07 MHz ( period = 2.958 ns )                    ; alu:inst|temp[10]                                                                     ; control_unit:inst2|address[2]     ; clk        ; clk      ; None                        ; None                      ; 2.762 ns                ;
; N/A                                     ; 338.41 MHz ( period = 2.955 ns )                    ; alu:inst|temp[13]                                                                     ; control_unit:inst2|address[1]     ; clk        ; clk      ; None                        ; None                      ; 2.759 ns                ;
; N/A                                     ; 338.98 MHz ( period = 2.950 ns )                    ; alu:inst|temp[10]                                                                     ; control_unit:inst2|address[1]     ; clk        ; clk      ; None                        ; None                      ; 2.754 ns                ;