original_signal.hier_info

来自「一种基于LUT的预失真方法。其中的一部分」· HIER_INFO 代码 · 共 2,340 行 · 第 1/5 页

DATAC[6] => OUTCT_1[6].DATAB
DATAC[7] => OUTCT_1[7].DATAA
DATAC[7] => OUTCT_1[7].DATAB
DATAC[8] => OUTCT_1[8].DATAA
DATAC[8] => OUTCT_1[8].DATAB
DATAC[9] => OUTCT_1[9].DATAA
DATAC[9] => OUTCT_1[9].DATAB
DATAC[10] => OUTCT_1[10].DATAA
DATAC[10] => OUTCT_1[10].DATAB
DATAC[11] => OUTCT_1[11].DATAA
DATAC[11] => OUTCT_1[11].DATAB
DATAC[12] => OUTCT_1[12].DATAA
DATAC[12] => OUTCT_1[12].DATAB
OUTS[0] <= OUTS[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTS[1] <= OUTS[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTS[2] <= OUTS[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTS[3] <= OUTS[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTS[4] <= OUTS[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTS[5] <= OUTS[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTS[6] <= OUTS[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTS[7] <= OUTS[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTS[8] <= OUTS[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTS[9] <= OUTS[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTS[10] <= OUTS[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTS[11] <= OUTS[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTS[12] <= OUTS[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTS[13] <= OUTS[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTC[0] <= OUTC[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTC[1] <= OUTC[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTC[2] <= OUTC[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTC[3] <= OUTC[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTC[4] <= OUTC[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTC[5] <= OUTC[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTC[6] <= OUTC[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTC[7] <= OUTC[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTC[8] <= OUTC[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTC[9] <= OUTC[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTC[10] <= OUTC[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTC[11] <= OUTC[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTC[12] <= OUTC[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
OUTC[13] <= OUTC[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE


|original_signal|dds2ch:inst3|out:U_out|addo:U_addo
dataa[0] => Add0.IN28
dataa[1] => Add0.IN27
dataa[2] => Add0.IN26
dataa[3] => Add0.IN25
dataa[4] => Add0.IN24
dataa[5] => Add0.IN23
dataa[6] => Add0.IN22
dataa[7] => Add0.IN21
dataa[8] => Add0.IN20
dataa[9] => Add0.IN19
dataa[10] => Add0.IN18
dataa[11] => Add0.IN17
dataa[12] => Add0.IN16
dataa[13] => Add0.IN15
result[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE


|original_signal|dds2ch:inst3|out:U_out|addo:U1_addo
dataa[0] => Add0.IN28
dataa[1] => Add0.IN27
dataa[2] => Add0.IN26
dataa[3] => Add0.IN25
dataa[4] => Add0.IN24
dataa[5] => Add0.IN23
dataa[6] => Add0.IN22
dataa[7] => Add0.IN21
dataa[8] => Add0.IN20
dataa[9] => Add0.IN19
dataa[10] => Add0.IN18
dataa[11] => Add0.IN17
dataa[12] => Add0.IN16
dataa[13] => Add0.IN15
result[0] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[1] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[2] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[3] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[4] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[5] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[6] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[7] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[8] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[9] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[10] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[11] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[12] <= Add0.DB_MAX_OUTPUT_PORT_TYPE
result[13] <= Add0.DB_MAX_OUTPUT_PORT_TYPE


|original_signal|frecontr:inst2
clk => i[5].CLK
clk => i[4].CLK
clk => i[3].CLK
clk => i[2].CLK
clk => i[1].CLK
clk => i[0].CLK
clk => fren~reg0.CLK
rstn => i[5].ACLR
rstn => i[4].ACLR
rstn => i[3].ACLR
rstn => i[2].ACLR
rstn => i[1].ACLR
rstn => i[0].ACLR
rstn => fren~reg0.ACLR
freqword[0] <= <GND>
freqword[1] <= <GND>
freqword[2] <= <GND>
freqword[3] <= <GND>
freqword[4] <= <VCC>
freqword[5] <= <VCC>
freqword[6] <= <GND>
freqword[7] <= <GND>
freqword[8] <= <GND>
freqword[9] <= <VCC>
freqword[10] <= <VCC>
freqword[11] <= <GND>
freqword[12] <= <GND>
freqword[13] <= <VCC>
freqword[14] <= <GND>
freqword[15] <= <VCC>
freqword[16] <= <GND>
freqword[17] <= <GND>
freqword[18] <= <VCC>
freqword[19] <= <GND>
freqword[20] <= <GND>
freqword[21] <= <VCC>
freqword[22] <= <GND>
freqword[23] <= <VCC>
freqword[24] <= <GND>
freqword[25] <= <GND>
freqword[26] <= <GND>
freqword[27] <= <VCC>
freqword[28] <= <GND>
freqword[29] <= <GND>
freqword[30] <= <VCC>
freqword[31] <= <GND>
fren <= fren~reg0.DB_MAX_OUTPUT_PORT_TYPE


|original_signal|altpll0:inst6
inclk0 => sub_wire4[0].IN1
c0 <= altpll:altpll_component.clk
c1 <= altpll:altpll_component.clk


|original_signal|altpll0:inst6|altpll:altpll_component
inclk[0] => altpll_ena1:auto_generated.inclk[0]
inclk[1] => altpll_ena1:auto_generated.inclk[1]
fbin => ~NO_FANOUT~
pllena => ~NO_FANOUT~
clkswitch => ~NO_FANOUT~
areset => ~NO_FANOUT~
pfdena => ~NO_FANOUT~
clkena[0] => ~NO_FANOUT~
clkena[1] => ~NO_FANOUT~
clkena[2] => ~NO_FANOUT~
clkena[3] => ~NO_FANOUT~
clkena[4] => ~NO_FANOUT~
clkena[5] => ~NO_FANOUT~
extclkena[0] => ~NO_FANOUT~
extclkena[1] => ~NO_FANOUT~
extclkena[2] => ~NO_FANOUT~
extclkena[3] => ~NO_FANOUT~
scanclk => ~NO_FANOUT~
scanclkena => ~NO_FANOUT~
scanaclr => ~NO_FANOUT~
scanread => ~NO_FANOUT~
scanwrite => ~NO_FANOUT~
scandata => ~NO_FANOUT~
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~
phaseupdown => ~NO_FANOUT~
phasestep => ~NO_FANOUT~
configupdate => ~NO_FANOUT~
fbmimicbidir <= <GND>
clk[0] <= clk[0]~4.DB_MAX_OUTPUT_PORT_TYPE
clk[1] <= clk[1]~3.DB_MAX_OUTPUT_PORT_TYPE
clk[2] <= clk[2]~2.DB_MAX_OUTPUT_PORT_TYPE
clk[3] <= clk[3]~1.DB_MAX_OUTPUT_PORT_TYPE
clk[4] <= clk[4]~0.DB_MAX_OUTPUT_PORT_TYPE
extclk[0] <= <GND>
extclk[1] <= <GND>
extclk[2] <= <GND>
extclk[3] <= <GND>
clkbad[0] <= <GND>
clkbad[1] <= <GND>
enable1 <= <GND>
enable0 <= <GND>
activeclock <= <GND>
clkloss <= <GND>
locked <= <GND>
scandataout <= <GND>
scandone <= <GND>
sclkout0 <= <GND>
sclkout1 <= <GND>
phasedone <= <GND>
vcooverrange <= <GND>
vcounderrange <= <GND>
fbout <= <GND>


|original_signal|altpll0:inst6|altpll:altpll_component|altpll_ena1:auto_generated
clk[0] <= pll1.CLK
clk[1] <= pll1.CLK1
clk[2] <= pll1.CLK2
clk[3] <= pll1.CLK3
clk[4] <= pll1.CLK4
inclk[0] => pll1.CLK
inclk[1] => pll1.CLK1
phasecounterselect[0] => ~NO_FANOUT~
phasecounterselect[1] => ~NO_FANOUT~
phasecounterselect[2] => ~NO_FANOUT~
phasecounterselect[3] => ~NO_FANOUT~


|original_signal|mod:inst4
ibase[0] => ~NO_FANOUT~
ibase[1] => ~NO_FANOUT~
ibase[2] => ~NO_FANOUT~
ibase[3] => ~NO_FANOUT~
ibase[4] => ~NO_FANOUT~
ibase[5] => ~NO_FANOUT~
ibase[6] => ~NO_FANOUT~
ibase[7] => Mult0.IN8
ibase[8] => Mult0.IN7
ibase[9] => Mult0.IN6
ibase[10] => Mult0.IN5
ibase[11] => Mult0.IN4
ibase[12] => Mult0.IN3
ibase[13] => Mult0.IN2
ibase[14] => Mult0.IN1
ibase[15] => Mult0.IN0
qbase[0] => ~NO_FANOUT~
qbase[1] => ~NO_FANOUT~
qbase[2] => ~NO_FANOUT~
qbase[3] => ~NO_FANOUT~
qbase[4] => ~NO_FANOUT~
qbase[5] => ~NO_FANOUT~
qbase[6] => ~NO_FANOUT~
qbase[7] => Mult1.IN8
qbase[8] => Mult1.IN7
qbase[9] => Mult1.IN6
qbase[10] => Mult1.IN5
qbase[11] => Mult1.IN4
qbase[12] => Mult1.IN3
qbase[13] => Mult1.IN2
qbase[14] => Mult1.IN1
qbase[15] => Mult1.IN0
qtran[0] => ~NO_FANOUT~
qtran[1] => ~NO_FANOUT~
qtran[2] => ~NO_FANOUT~
qtran[3] => ~NO_FANOUT~
qtran[4] => ~NO_FANOUT~
qtran[5] => Mult0.IN17
qtran[6] => Mult0.IN16
qtran[7] => Mult0.IN15
qtran[8] => Mult0.IN14
qtran[9] => Mult0.IN13
qtran[10] => Mult0.IN12
qtran[11] => Mult0.IN11
qtran[12] => Mult0.IN10
qtran[13] => Mult0.IN9
itran[0] => ~NO_FANOUT~
itran[1] => ~NO_FANOUT~
itran[2] => ~NO_FANOUT~
itran[3] => ~NO_FANOUT~
itran[4] => ~NO_FANOUT~
itran[5] => Mult1.IN17
itran[6] => Mult1.IN16
itran[7] => Mult1.IN15
itran[8] => Mult1.IN14
itran[9] => Mult1.IN13
itran[10] => Mult1.IN12
itran[11] => Mult1.IN11
itran[12] => Mult1.IN10
itran[13] => Mult1.IN9
clk => rfout[18].CLK
clk => rfout[17].CLK
clk => rfout[16].CLK
clk => rfout[15].CLK
clk => rfout[14].CLK
clk => rfout[13].CLK
clk => rfout[12].CLK
clk => rfout[11].CLK
clk => rfout[10].CLK
clk => rfout[9].CLK
clk => rfout[8].CLK
clk => rfout[7].CLK
clk => lposition[17].CLK
clk => lposition[16].CLK
clk => lposition[15].CLK
clk => lposition[14].CLK
clk => lposition[13].CLK
clk => lposition[12].CLK
clk => lposition[11].CLK
clk => lposition[10].CLK
clk => lposition[9].CLK
clk => lposition[8].CLK
clk => lposition[7].CLK
clk => lposition[6].CLK
clk => lposition[5].CLK
clk => lposition[4].CLK
clk => lposition[3].CLK
clk => lposition[2].CLK
clk => lposition[1].CLK
clk => lposition[0].CLK
clk => rposition[17].CLK
clk => rposition[16].CLK
clk => rposition[15].CLK
clk => rposition[14].CLK
clk => rposition[13].CLK
clk => rposition[12].CLK
clk => rposition[11].CLK
clk => rposition[10].CLK
clk => rposition[9].CLK
clk => rposition[8].CLK
clk => rposition[7].CLK
clk => rposition[6].CLK
clk => rposition[5].CLK
clk => rposition[4].CLK
clk => rposition[3].CLK
clk => rposition[2].CLK
clk => rposition[1].CLK
clk => rposition[0].CLK
rstn => rfout[18].ACLR
rstn => rfout[17].ACLR
rstn => rfout[16].ACLR
rstn => rfout[15].ACLR
rstn => rfout[14].ACLR
rstn => rfout[13].ACLR
rstn => rfout[12].ACLR
rstn => rfout[11].ACLR
rstn => rfout[10].ACLR
rstn => rfout[9].ACLR
rstn => rfout[8].ACLR
rstn => rfout[7].ACLR
rstn => rposition[0].ENA
rstn => lposition[17].ENA
rstn => lposition[16].ENA
rstn => lposition[15].ENA
rstn => lposition[14].ENA
rstn => lposition[13].ENA
rstn => lposition[12].ENA
rstn => lposition[11].ENA
rstn => lposition[10].ENA
rstn => lposition[9].ENA
rstn => lposition[8].ENA
rstn => lposition[7].ENA
rstn => lposition[6].ENA
rstn => lposition[5].ENA
rstn => lposition[4].ENA
rstn => lposition[3].ENA
rstn => lposition[2].ENA
rstn => lposition[1].ENA
rstn => lposition[0].ENA
rstn => rposition[17].ENA
rstn => rposition[16].ENA
rstn => rposition[15].ENA
rstn => rposition[14].ENA
rstn => rposition[13].ENA
rstn => rposition[12].ENA
rstn => rposition[11].ENA
rstn => rposition[10].ENA
rstn => rposition[9].ENA
rstn => rposition[8].ENA
rstn => rposition[7].ENA
rstn => rposition[6].ENA
rstn => rposition[5].ENA
rstn => rposition[4].ENA
rstn => rposition[3].ENA
rstn => rposition[2].ENA
rstn => rposition[1].ENA
rf[0] <= rfout[7].DB_MAX_OUTPUT_PORT_TYPE
rf[1] <= rfout[8].DB_MAX_OUTPUT_PORT_TYPE
rf[2] <= rfout[9].DB_MAX_OUTPUT_PORT_TYPE
rf[3] <= rfout[10].DB_MAX_OUTPUT_PORT_TYPE
rf[4] <= rfout[11].DB_MAX_OUTPUT_PORT_TYPE
rf[5] <= rfout[12].DB_MAX_OUTPUT_PORT_TYPE
rf[6] <= rfout[13].DB_MAX_OUTPUT_PORT_TYPE
rf[7] <= rfout[14].DB_MAX_OUTPUT_PORT_TYPE
rf[8] <= rfout[15].DB_MAX_OUTPUT_PORT_TYPE
rf[9] <= rfout[16].DB_MAX_OUTPUT_PORT_TYPE
rf[10] <= rfout[17].DB_MAX_OUTPUT_PORT_TYPE
rf[11] <= rfout[18].DB_MAX_OUTPUT_PORT_TYPE


|original_signal|FIRInterp:inst8
RST => LTDt[33].ACLR
RST => LTDt[32].ACLR
RST => LTDt[31].ACLR
RST => LTDt[30].ACLR
RST => LTDt[29].ACLR
RST => LTDt[28].ACLR
RST => LTDt[27].ACLR
RST => LTDt[26].ACLR
RST => LTDt[25].ACLR
RST => LTDt[24].ACLR
RST => LTDt[23].ACLR
RST => LTDt[22].ACLR
RST => LTDt[21].ACLR
RST => LTDt[20].ACLR
RST => LTDt[19].ACLR
RST => LTDt[18].ACLR
RST => LTDt[17].ACLR
RST => LTDt[16].ACLR
RST => LTDt[15].ACLR
RST => LTDt[14].ACLR
RST => LTDt[13].ACLR
RST => LTDt[12].ACLR
RST => LTDt[11].ACLR
RST => LTDt[10].ACLR
RST => LTDt[9].ACLR
RST => LTDt[8].ACLR
RST => LTDt[7].ACLR
RST => LTDt[6].ACLR
RST => LTDt[5].ACLR
RST => LTDt[4].ACLR
RST => LTDt[3].ACLR
RST => LTDt[2].ACLR
RST => LTDt[1].ACLR
RST => LTDt[0].ACLR
RST => RTDt[33].ACLR
RST => RTDt[32].ACLR
RST => RTDt[31].ACLR
RST => RTDt[30].ACLR
RST => RTDt[29].ACLR
RST => RTDt[28].ACLR
RST => RTDt[27].ACLR
RST => RTDt[26].ACLR
RST => RTDt[25].ACLR
RST => RTDt[24].ACLR
RST => RTDt[23].ACLR
RST => RTDt[22].ACLR
RST => RTDt[21].ACLR
RST => RTDt[20].ACLR
RST => RTDt[19].ACLR
RST => RTDt[18].ACLR
RST => RTDt[17].ACLR
RST => RTDt[16].ACLR
RST => RTDt[15].ACLR
RST => RTDt[14].ACLR
RST => RTDt[13].ACLR
RST => RTDt[12].ACLR
RST => RTDt[11].ACLR
RST => RTDt[10].ACLR
RST => RTDt[9].ACLR
RST => RTDt[8].ACLR
RST => RTDt[7].ACLR
RST => RTDt[6].ACLR
RST => R