fifo.v

verilog source code for uart design

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:05:59 02/03/2009 
// Design Name: 
// Module Name:    FIFO 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module FIFO(wr, reset,clk,rd,data,full, empty,data1);

	input wr,rd,clk,reset;
	input [3:0] data;
	output reg full,empty;
	output reg [3:0] data1;
	
	
	integer current = 0;
	integer temp = 0;
		
	reg  [3:0]memory[15:0];
	
	
	
	always@ (posedge clk) begin
	
	if (reset == 1) begin
	 data1 = 0;
	 empty = 0;
	 full = 0;
	 end
	 
	if (wr == 1) 
	begin
		if(current == 15)
			full = 1;
		else 
			begin 
				full = 0;
				empty = 0;
				memory[current] = data;				
				current = current + 1;
			end
	end

	else if (rd == 1)
	begin
		if(current == 0)
			begin 
				data1 = 0;
				empty = 1;
			end
		else if (current == 1)
			begin
				empty = 0;
				full = 0;
				data1 = memory[0];
				current = current - 1;
			end
		else
			begin
				empty = 0;
				full = 0;
				data1 = memory[0];
				for (temp = 0; temp<15 ; temp = temp + 1)
					memory[temp] = memory[temp + 1];
				current = current - 1;
			end
			
	end		

end

endmodule