test.v

verilog source code for uart design

`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:44:05 02/03/2009
// Design Name:   FIFO
// Module Name:   C:/Xilinx/digi/lab3/test.v
// Project Name:  lab3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: FIFO
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module test_v;

	// Inputs
	reg wr;
	reg rd;
	reg [7:0] ;

	// Outputs
	wire full;
	wire empty;
	wire [7:0] ;

	// Instantiate the Unit Under Test (UUT)
	FIFO uut (
		.wr(wr), 
		.rd(rd), 
		.(), 
		.full(full), 
		.empty(empty), 
		.()
	);

	initial begin
		// Initialize Inputs
		wr = 0;
		rd = 0;
		 = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here

	end
      
endmodule