test1.stx

来自「verilog source code for uart design」· STX 代码 · 共 25 行

Release 8.2i - xst I.31
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.25 s | Elapsed : 0.00 / 0.00 s
 
--> 
=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "test1.v" in library work
Module <test1> compiled
No errors in compilation
Analysis of file <"test1.prj"> succeeded.
 
CPU : 0.02 / 0.27 s | Elapsed : 0.00 / 0.00 s
 
--> 

Total memory usage is 108196 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    0 (   0 filtered)
Number of infos    :    0 (   0 filtered)