testfifo.v

verilog source code for uart design

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:54:26 02/03/2009 
// Design Name: 
// Module Name:    testfifo 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module testfifo();
wire full,empty;
wire [3:0] data1;

reg wr,rd,clk,reset;
reg [3:0] data; 

FIFO kp(wr,reset, clk,rd,data,full, empty,data1);


initial begin

#100;
clk = 0;
#100;
clk = 1;
rd = 1;
#100;
clk = 0;
rd = 0;
#100;
clk = 1;
wr = 1;
data = 4'b0001;
#100;
clk = 0;
wr = 0;
data = 4'b0010;
#100;

clk = 1;
wr = 1;
data = 4'b0010;
#100;
clk = 0;
wr = 0;
data = 4'b0011;
#100;
clk = 1;
wr = 1;
data = 4'b0011;
#100;
clk =0;
wr = 0;
#100;
clk = 1;
rd = 1;
#100;
clk = 0;
rd = 1;
#100;
clk = 1;
rd = 1;
#100;
clk = 0;
rd = 1;
#100;
clk = 1;
rd = 1;
#100;
clk = 0;
rd = 1;
#100;
clk = 1;
rd = 1;
#100;
clk = 0;
rd = 1;
#100;
end
endmodule