fifo.par

verilog source code for uart design

Release 8.2i par I.31
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.

LAB20520::  Tue Feb 03 16:17:02 2009

par -w -intstyle ise -ol std -t 1 FIFO_map.ncd FIFO.ncd FIFO.pcf 


Constraints file: FIFO.pcf.
Loading device for application Rf_Device from file '4vlx100.nph' in environment C:\Xilinx.
   "FIFO" is an NCD, version 3.1, device xc4vlx100, package ff1148, speed -12
This design is using the default stepping level (major silicon revision) for this device (1). Unless your design is
targeted at devices of this stepping level, it is recommended that you explicitly specify the stepping level of the
parts you will be using. This will allow the tools to take advantage of any available performance and functional
enhancements for this device. The latest stepping level for this device is '2'. Additional information on "stepping
level" is available at support.xilinx.com.

Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)

INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
   -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
   internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
   the fastest runtime, set the effort level to "std".  For best performance, set the effort level to "high". For a
   balance between the fastest runtime and best performance, set the effort level to "med".

Device speed data version:  "PRODUCTION 1.60 2006-05-03".


Device Utilization Summary:

   Number of BUFGs                     1 out of 32      3%
   Number of External IOBs            14 out of 768     1%
      Number of LOCed IOBs             0 out of 14      0%

   Number of OLOGICs                   4 out of 960     1%
   Number of Slices                  161 out of 49152   1%
      Number of SLICEMs                0 out of 24576   0%



Overall effort level (-ol):   Standard 
Placer effort level (-pl):    High 
Placer cost table entry (-t): 1
Router effort level (-rl):    Standard 


Starting Placer

Phase 1.1
Phase 1.1 (Checksum:989b25) REAL time: 18 secs 

Phase 2.31
Phase 2.31 (Checksum:1312cfe) REAL time: 19 secs 

Phase 3.2
.


Phase 3.2 (Checksum:1c9c37d) REAL time: 1 mins 11 secs 

Phase 4.30
Phase 4.30 (Checksum:26259fc) REAL time: 1 mins 11 secs 

Phase 5.3
Phase 5.3 (Checksum:2faf07b) REAL time: 1 mins 12 secs 

Phase 6.5
Phase 6.5 (Checksum:39386fa) REAL time: 1 mins 12 secs 

Phase 7.8
.....
......
....
....
....
..
Phase 7.8 (Checksum:a1df92) REAL time: 1 mins 13 secs 

Phase 8.5
Phase 8.5 (Checksum:4c4b3f8) REAL time: 1 mins 13 secs 

Phase 10.18
Phase 10.18 (Checksum:5f5e0f6) REAL time: 1 mins 15 secs 

Phase 11.27
Phase 11.27 (Checksum:68e7775) REAL time: 1 mins 15 secs 

Phase 12.5
Phase 12.5 (Checksum:7270df4) REAL time: 1 mins 15 secs 

Writing design to file FIFO.ncd


Total REAL time to Placer completion: 1 mins 15 secs 
Total CPU time to Placer completion: 1 mins 9 secs 

Starting Router

Phase 1: 923 unrouted;       REAL time: 1 mins 17 secs 

Phase 2: 819 unrouted;       REAL time: 2 mins 

Phase 3: 326 unrouted;       REAL time: 2 mins 

Phase 4: 326 unrouted; (20211)      REAL time: 2 mins 1 secs 

Phase 5: 335 unrouted; (0)      REAL time: 2 mins 1 secs 

Phase 6: 0 unrouted; (0)      REAL time: 2 mins 1 secs 

Phase 7: 0 unrouted; (0)      REAL time: 2 mins 1 secs 

Phase 8: 0 unrouted; (0)      REAL time: 2 mins 1 secs 

Phase 9: 0 unrouted; (0)      REAL time: 2 mins 1 secs 

Phase 10: 0 unrouted; (0)      REAL time: 2 mins 1 secs 

Total REAL time to Router completion: 2 mins 2 secs 
Total CPU time to Router completion: 1 mins 49 secs 

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

Generating "PAR" statistics.

**************************
Generating Clock Report
**************************

+---------------------+--------------+------+------+------------+-------------+
|        Clock Net    |   Resource   |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
|           clk_BUFGP |BUFGCTRL_X0Y22| No   |   59 |  0.304     |  2.316      |
+---------------------+--------------+------+------+------------+-------------+

* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.


   The Delay Summary Report


The NUMBER OF SIGNALS NOT COMPLETELY ROUTED for this design is: 0

   The AVERAGE CONNECTION DELAY for this design is:        1.251
   The MAXIMUM PIN DELAY IS:                               5.353
   The AVERAGE CONNECTION DELAY on the 10 WORST NETS is:   2.176

   Listing Pin Delays by value: (nsec)

    d < 1.00   < d < 2.00  < d < 3.00  < d < 4.00  < d < 6.00  d >= 6.00
   ---------   ---------   ---------   ---------   ---------   ---------
         591         123          64           0         117           0

Timing Score: 0

Asterisk (*) preceding a constraint indicates it was not met.
   This may be due to a setup or hold violation.

------------------------------------------------------------------------------------------------------
  Constraint                                | Requested  | Actual     | Logic  | Absolute   |Number of
                                            |            |            | Levels | Slack      |errors   
------------------------------------------------------------------------------------------------------
  Autotimespec constraint for clock net clk | N/A        | 4.429ns    | 6      | N/A        | N/A     
  _BUFGP                                    |            |            |        |            |         
------------------------------------------------------------------------------------------------------


All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the 
   constraint does not cover any paths or that it has no requested value.


Generating Pad Report.

All signals are completely routed.

Total REAL time to PAR completion: 2 mins 6 secs 
Total CPU time to PAR completion: 1 mins 51 secs 

Peak Memory Usage:  385 MB

Placement: Completed - No errors found.
Routing: Completed - No errors found.

Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1

Writing design to file FIFO.ncd



PAR done!