test1.v

verilog source code for uart design

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    14:44:47 02/03/2009 
// Design Name: 
// Module Name:    test1 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module test1();

wire full,empty;
wire [7:0] data1;

reg wr,rd,clk;
reg [7:0] data; 
initial begin

#10;
clk = 0;
#10;
clk = 1;
rd = 1;
#10;
clk = 0;
rd = 0;
#10;
clk = 1;
wr = 1;
data = 8'b10101010;
#10;
clk = 0;
wr = 0;
#10;
clk = 1;
wr = 1;
data = 8'b11111111;
#10;
clk =0;
wr = 0;
#10;
clk = 1;
rd = 1;
#10;

end


endmodule