fifo.syr

verilog source code for uart design

-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : FIFO.ngr
Top Level Output File Name         : FIFO
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : NO

Design Statistics
# IOs                              : 14

Cell Usage :
# BELS                             : 323
#      GND                         : 1
#      INV                         : 1
#      LUT2                        : 103
#      LUT2_D                      : 1
#      LUT3                        : 41
#      LUT3_D                      : 4
#      LUT4                        : 93
#      LUT4_D                      : 6
#      LUT4_L                      : 1
#      MUXCY                       : 38
#      MUXF5                       : 1
#      VCC                         : 1
#      XORCY                       : 32
# FlipFlops/Latches                : 104
#      FD                          : 40
#      FDE                         : 64
# Clock Buffers                    : 1
#      BUFGP                       : 1
# IO Buffers                       : 13
#      IBUF                        : 7
#      OBUF                        : 6
=========================================================================

Device utilization summary:
---------------------------

Selected Device : 4vlx100ff1148-12 

 Number of Slices:                     129  out of  49152     0%  
 Number of Slice Flip Flops:           104  out of  98304     0%  
 Number of 4 input LUTs:               250  out of  98304     0%  
 Number of IOs:                         14
 Number of bonded IOBs:                 14  out of    768     1%  
 Number of GCLKs:                        1  out of     32     3%  


=========================================================================
TIMING REPORT

NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
      FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
      GENERATED AFTER PLACE-and-ROUTE.

Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal                       | Clock buffer(FF name)  | Load  |
-----------------------------------+------------------------+-------+
clk                                | BUFGP                  | 104   |
-----------------------------------+------------------------+-------+

Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design

Timing Summary:
---------------
Speed Grade: -12

   Minimum period: 3.915ns (Maximum Frequency: 255.438MHz)
   Minimum input arrival time before clock: 4.911ns
   Maximum output required time after clock: 3.935ns
   Maximum combinational path delay: No path found

Timing Detail:
--------------
All values displayed in nanoseconds (ns)

=========================================================================
Timing constraint: Default period analysis for Clock 'clk'
  Clock period: 3.915ns (frequency: 255.438MHz)
  Total number of paths / destination ports: 5866 / 164
-------------------------------------------------------------------------
Delay:               3.915ns (Levels of Logic = 11)
  Source:            current_23 (FF)
  Destination:       current_9 (FF)
  Source Clock:      clk rising
  Destination Clock: clk rising

  Data Path: current_23 to current_9
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               3   0.272   0.581  current_23 (current_23)
     LUT4:I0->O            1   0.147   0.000  _cmp_eq00001_wg_lut<0> (N191)
     MUXCY:S->O            1   0.278   0.000  _cmp_eq00001_wg_cy<0> (_cmp_eq00001_wg_cy<0>)
     MUXCY:CI->O           1   0.034   0.000  _cmp_eq00001_wg_cy<1> (_cmp_eq00001_wg_cy<1>)
     MUXCY:CI->O           1   0.034   0.000  _cmp_eq00001_wg_cy<2> (_cmp_eq00001_wg_cy<2>)
     MUXCY:CI->O           1   0.034   0.000  _cmp_eq00001_wg_cy<3> (_cmp_eq00001_wg_cy<3>)
     MUXCY:CI->O           1   0.034   0.000  _cmp_eq00001_wg_cy<4> (_cmp_eq00001_wg_cy<4>)
     MUXCY:CI->O           1   0.034   0.000  _cmp_eq00001_wg_cy<5> (_cmp_eq00001_wg_cy<5>)
     MUXCY:CI->O           6   0.280   0.485  _cmp_eq00001_wg_cy<6> (_cmp_eq00001_wg_cy<6>)
     LUT4_D:I2->O          3   0.147   0.463  _not0039_SW0 (N243)
     LUT4_D:I2->O          7   0.147   0.501  _not0039_1 (_not00391)
     LUT3:I2->O            1   0.147   0.000  current_21_rstpot (N285)
     FD:D                      0.297          current_21
    ----------------------------------------
    Total                      3.915ns (1.885ns logic, 2.030ns route)
                                       (48.1% logic, 51.9% route)

=========================================================================
Timing constraint: Default OFFSET IN BEFORE for Clock 'clk'
  Total number of paths / destination ports: 1097 / 168
-------------------------------------------------------------------------
Offset:              4.911ns (Levels of Logic = 35)
  Source:            wr (PAD)
  Destination:       current_31 (FF)
  Destination Clock: clk rising

  Data Path: wr to current_31
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     IBUF:I->O           117   0.754   1.140  wr_IBUF (wr_IBUF)
     INV:I->O              1   0.322   0.394  wr_inv_INV_0 (N6)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<0> (Mcount_current_cy<0>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<1> (Mcount_current_cy<1>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<2> (Mcount_current_cy<2>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<3> (Mcount_current_cy<3>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<4> (Mcount_current_cy<4>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<5> (Mcount_current_cy<5>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<6> (Mcount_current_cy<6>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<7> (Mcount_current_cy<7>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<8> (Mcount_current_cy<8>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<9> (Mcount_current_cy<9>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<10> (Mcount_current_cy<10>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<11> (Mcount_current_cy<11>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<12> (Mcount_current_cy<12>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<13> (Mcount_current_cy<13>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<14> (Mcount_current_cy<14>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<15> (Mcount_current_cy<15>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<16> (Mcount_current_cy<16>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<17> (Mcount_current_cy<17>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<18> (Mcount_current_cy<18>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<19> (Mcount_current_cy<19>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<20> (Mcount_current_cy<20>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<21> (Mcount_current_cy<21>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<22> (Mcount_current_cy<22>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<23> (Mcount_current_cy<23>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<24> (Mcount_current_cy<24>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<25> (Mcount_current_cy<25>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<26> (Mcount_current_cy<26>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<27> (Mcount_current_cy<27>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<28> (Mcount_current_cy<28>)
     MUXCY:CI->O           1   0.034   0.000  Mcount_current_cy<29> (Mcount_current_cy<29>)
     MUXCY:CI->O           0   0.034   0.000  Mcount_current_cy<30> (Mcount_current_cy<30>)
     XORCY:CI->O           1   0.273   0.529  Mcount_current_xor<31> (Result<31>)
     LUT3:I1->O            1   0.147   0.000  current_31_rstpot (N295)
     FD:D                      0.297          current_31
    ----------------------------------------
    Total                      4.911ns (2.847ns logic, 2.064ns route)
                                       (58.0% logic, 42.0% route)

=========================================================================
Timing constraint: Default OFFSET OUT AFTER for Clock 'clk'
  Total number of paths / destination ports: 6 / 6
-------------------------------------------------------------------------
Offset:              3.935ns (Levels of Logic = 1)
  Source:            empty (FF)
  Destination:       empty (PAD)
  Source Clock:      clk rising

  Data Path: empty to empty
                                Gate     Net
    Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
    ----------------------------------------  ------------
     FD:C->Q               2   0.272   0.408  empty (empty_OBUF)
     OBUF:I->O                 3.255          empty_OBUF (empty)
    ----------------------------------------
    Total                      3.935ns (3.527ns logic, 0.408ns route)
                                       (89.6% logic, 10.4% route)

=========================================================================
CPU : 18.30 / 18.63 s | Elapsed : 18.00 / 18.00 s
 
--> 

Total memory usage is 329488 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    1 (   0 filtered)
Number of infos    :    2 (   0 filtered)