fifo.syr

verilog source code for uart design

Release 8.2i - xst I.31
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: FIFO.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report
     9.1) Device utilization summary
     9.2) TIMING REPORT


=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "FIFO.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "FIFO"
Output Format                      : NGC
Target Device                      : xc4vlx100-12-ff1148

---- Source Options
Top Module Name                    : FIFO
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
FSM Style                          : lut
RAM Extraction                     : Yes
RAM Style                          : Auto
ROM Extraction                     : Yes
Mux Style                          : Auto
Decoder Extraction                 : YES
Priority Encoder Extraction        : YES
Shift Register Extraction          : YES
Logical Shifter Extraction         : YES
XOR Collapsing                     : YES
ROM Style                          : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES
Automatic Register Balancing       : No

---- Target Options
Add IO Buffers                     : YES
Global Maximum Fanout              : 500
Add Generic Clock Buffer(BUFG)     : 32
Number of Regional Clock Buffers   : 48
Register Duplication               : YES
Slice Packing                      : YES
Pack IO Registers into IOBs        : auto
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : NO
RTL Output                         : Yes
Global Optimization                : AllClockNets
Write Timing Constraints           : NO
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain
Slice Utilization Ratio            : 100
DSP48 Utilization Ratio            : 100
Slice Utilization Ratio Delta      : 5

---- Other Options
lso                                : FIFO.lso
Read Cores                         : YES
cross_clock_analysis               : NO
verilog2001                        : YES
safe_implementation                : No
use_dsp48                          : auto
Optimize Instantiated Primitives   : NO
use_clock_enable                   : Auto
use_sync_set                       : Auto
use_sync_reset                     : Auto

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling verilog file "FIFO.v" in library work
Module <FIFO> compiled
No errors in compilation
Analysis of file <"FIFO.prj"> succeeded.
 

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for module <FIFO> in library <work>.

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing top module <FIFO>.
Module <FIFO> is correct for synthesis.
 

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <FIFO>.
    Related source file is "FIFO.v".
WARNING:Xst:1872 - Variable <temp> is used but never assigned.
    Found 4x1-bit ROM for signal <$mux0002>.
    Found 4-bit register for signal <data1>.
    Found 1-bit register for signal <empty>.
    Found 1-bit register for signal <full>.
    Found 32-bit updown counter for signal <current>.
    Found 64-bit register for signal <memory>.
    Summary:
	inferred   1 ROM(s).
	inferred   1 Counter(s).
	inferred  70 D-type flip-flop(s).
Unit <FIFO> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 4x1-bit ROM                                           : 1
# Counters                                             : 1
 32-bit updown counter                                 : 1
# Registers                                            : 19
 1-bit register                                        : 2
 4-bit register                                        : 17

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Loading device for application Rf_Device from file '4vlx100.nph' in environment C:\Xilinx.
INFO:Xst:1647 - Data output of ROM <Mrom__mux0002> is tied to register <full>.
INFO:Xst:2506 - In order to maximize performance and save block RAM resources, this small ROM will be implemented on LUT. If you want to force its implementation on block, use option/constraint rom_style.

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# ROMs                                                 : 1
 4x1-bit ROM                                           : 1
# Counters                                             : 1
 32-bit updown counter                                 : 1
# Registers                                            : 70
 Flip-Flops                                            : 70

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <FIFO> ...

Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block FIFO, actual ratio is 0.
FlipFlop current_0 has been replicated 1 time(s)
FlipFlop current_2 has been replicated 1 time(s)

Final Macro Processing ...

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 104
 Flip-Flops                                            : 104

=========================================================================

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status