da_tlc5620.map.qmsg

用verilong hdl语言编写的数据采样程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Nov 27 19:35:14 2008 " "Info: Processing started: Thu Nov 27 19:35:14 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off DA_TLC5620 -c DA_TLC5620 " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off DA_TLC5620 -c DA_TLC5620" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_INGORE_DANGLING_COMMA" "DA_TLC5620.v(54) " "Warning (10275): Verilog HDL Module Instantiation warning at DA_TLC5620.v(54): ignored dangling comma in List of Port Connections" {  } { { "DA_TLC5620.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DA_TLC5620.v" 54 0 0 } }  } 0 10275 "Verilog HDL Module Instantiation warning at %1!s!: ignored dangling comma in List of Port Connections" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DA_TLC5620.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file DA_TLC5620.v" { { "Info" "ISGN_ENTITY_NAME" "1 DA_TLC5620 " "Info: Found entity 1: DA_TLC5620" {  } { { "DA_TLC5620.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DA_TLC5620.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Warning" "WVRFX_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "dac_test.v(83) " "Warning (10268): Verilog HDL information at dac_test.v(83): Always Construct contains both blocking and non-blocking assignments" {  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 83 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: Always Construct contains both blocking and non-blocking assignments" 1 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dac_test.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file dac_test.v" { { "Info" "ISGN_ENTITY_NAME" "1 dac_test " "Info: Found entity 1: dac_test" {  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 6 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "DA_TLC5620 " "Info: Elaborating entity \"DA_TLC5620\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "tlc5620.v 1 1 " "Warning: Using design file tlc5620.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 tlc5620 " "Info: Found entity 1: tlc5620" {  } { { "tlc5620.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/tlc5620.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "tlc5620 tlc5620:M1 " "Info: Elaborating entity \"tlc5620\" for hierarchy \"tlc5620:M1\"" {  } { { "DA_TLC5620.v" "M1" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DA_TLC5620.v" 42 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "dac_test dac_test:M2 " "Info: Elaborating entity \"dac_test\" for hierarchy \"dac_test:M2\"" {  } { { "DA_TLC5620.v" "M2" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DA_TLC5620.v" 54 -1 0 } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Info" "IVRFX_VERI_ALMOST_ONEHOT_CASE_STATEMENT" "dac_test.v(68) " "Info (10264): Verilog HDL Case Statement information at dac_test.v(68): all case item expressions in this case statement are onehot" {  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 68 0 0 } }  } 0 10264 "Verilog HDL Case Statement information at %1!s!: all case item expressions in this case statement are onehot" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 dac_test.v(95) " "Warning (10230): Verilog HDL assignment warning at dac_test.v(95): truncated value with size 32 to match size of target (8)" {  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 95 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 dac_test.v(96) " "Warning (10230): Verilog HDL assignment warning at dac_test.v(96): truncated value with size 32 to match size of target (8)" {  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 96 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 dac_test.v(97) " "Warning (10230): Verilog HDL assignment warning at dac_test.v(97): truncated value with size 32 to match size of target (8)" {  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 97 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 dac_test.v(98) " "Warning (10230): Verilog HDL assignment warning at dac_test.v(98): truncated value with size 32 to match size of target (8)" {  } { { "dac_test.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/dac_test.v" 98 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DIFF_ONLY_IN_CASE" "CH451_DISPLAY CH451_Display DISPLAY.v(67) " "Info (10281): Verilog HDL Declaration information at DISPLAY.v(67): object \"CH451_DISPLAY\" differs only in case from object \"CH451_Display\" in the same scope" {  } { { "DISPLAY.v" "" { Text "E:/FPGA/工程/Logic design/DA_TLC5620/DA_TLC5620_pro/DISPLAY.v" 67 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0}