da_tlc5620.map.summary

来自「用verilong hdl语言编写的数据采样程序」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Thu Nov 27 19:35:44 2008
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : DA_TLC5620
Top-level Entity Name : DA_TLC5620
Family : Cyclone
Total logic elements : 832
Total pins : 11
Total virtual pins : 0
Total memory bits : 0
Total PLLs : 0