da_tlc5620.tan.summary

来自「用verilong hdl语言编写的数据采样程序」· SUMMARY 代码 · 共 57 行

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -1.355 ns
From           : key[0]
To             : dac_test:M2|channel[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 19.032 ns
From           : tlc5620:M1|counter[0]
To             : dac_data
From Clock     : clk
To Clock       : --
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 4.104 ns
From           : key[1]
To             : dac_test:M2|key1_r[0]
From Clock     : --
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 12.94 MHz ( period = 77.272 ns )
From           : dac_test:M2|data_code_r[5]
To             : dac_test:M2|display_data1[3]
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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