tlc5620.v

用verilong hdl语言编写的数据采样程序

module tlc5620(clk,rst,write_n,wr_data,dac_clk,dac_data,dac_load,dac_ldac);

  input        clk;
  input        rst;
  input        write_n;
  input[10:0]  wr_data;

  output       dac_clk;
  output       dac_data;
  output       dac_load;
  output       dac_ldac;

  wire         dac_done;

  reg          dac_clk_r;
  reg          dac_data_r;
  reg [5:0]    counter;
  reg [31:0]   DCLK_DIV;

parameter CLK_FREQ = 'D50_000_000;//系统时钟50MHZ
parameter DCLK_FREQ = 'D1_000_000;//AD_CLK输出时钟1M/2HZ

always @(posedge clk)
  if(DCLK_DIV < (CLK_FREQ / DCLK_FREQ))
    DCLK_DIV <= DCLK_DIV+1'b1;
  else
    begin 
      DCLK_DIV <= 0;
      dac_clk_r <= ~dac_clk_r;
    end

always @(posedge dac_clk_r or negedge rst)
 begin
   if(!rst)
      counter <= 0;
   else 
    if(counter<='d13)
     counter <= counter + 1'b1;
    else
      counter <= 0;
end

assign dac_load = (counter == 4'd12) ? 1'b0 : 1'b1;  
assign dac_clk = (counter > 'd0 && counter < 'd12) ? dac_clk_r : 1'b0;
assign dac_ldac = (counter == 4'd13) ? 1'b0 : 1'b1; 
assign dac_done =  (counter <= 4'd11) ? 1'b0 : 1'b1;
assign dac_data = dac_data_r;

/*先高位，把11位数据传输给DAC芯片*/
always @(counter[3:0] or wr_data or dac_done or write_n)
  begin
   if(!dac_done && !write_n)
    case(counter[3:0])
     4'd1:  dac_data_r <= wr_data[10];
     4'd2:  dac_data_r <= wr_data[9];
     4'd3:  dac_data_r <= wr_data[8];
     4'd4:  dac_data_r <= wr_data[7];
     4'd5:  dac_data_r <= wr_data[6];
     4'd6:  dac_data_r <= wr_data[5];
     4'd7:  dac_data_r <= wr_data[4];
     4'd8:  dac_data_r <= wr_data[3];
     4'd9:  dac_data_r <= wr_data[2];
     4'd10: dac_data_r <= wr_data[1];
     4'd11: dac_data_r <= wr_data[0];
     default: dac_data_r <= 1'b1;
    endcase
   else 
    dac_data_r <= 1'b1;
end

endmodule