tx.bsf

uart的vhdl实现

/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2004 Altera Corporation
Any  megafunction  design,  and related netlist (encrypted  or  decrypted),
support information,  device programming or simulation file,  and any other
associated  documentation or information  provided by  Altera  or a partner
under  Altera's   Megafunction   Partnership   Program  may  be  used  only
to program  PLD  devices (but not masked  PLD  devices) from  Altera.   Any
other  use  of such  megafunction  design,  netlist,  support  information,
device programming or simulation file,  or any other  related documentation
or information  is prohibited  for  any  other purpose,  including, but not
limited to  modification,  reverse engineering,  de-compiling, or use  with
any other  silicon devices,  unless such use is  explicitly  licensed under
a separate agreement with  Altera  or a megafunction partner.  Title to the
intellectual property,  including patents,  copyrights,  trademarks,  trade
secrets,  or maskworks,  embodied in any such megafunction design, netlist,
support  information,  device programming or simulation file,  or any other
related documentation or information provided by  Altera  or a megafunction
partner, remains with Altera, the megafunction partner, or their respective
licensors. No other licenses, including any licenses needed under any third
party's intellectual property, are provided herein.
*/
(header "symbol" (version "1.1"))
(symbol
	(rect 64 64 280 296)
	(text "TX" (rect 5 0 16 12)(font "Arial" ))
	(text "inst" (rect 16 200 33 212)(font "Arial" ))
	(port
		(pt 0 152)
		(input)
		(text "clk" (rect 0 0 14 12)(font "Arial" ))
		(text "clk" (rect 21 144 35 156)(font "Arial" ))
		(line (pt 0 152)(pt 16 152)(line_width 1))
	)
	(port
		(pt 0 136)
		(input)
		(text "reset" (rect 0 0 24 12)(font "Arial" ))
		(text "reset" (rect 21 128 45 140)(font "Arial" ))
		(line (pt 0 136)(pt 16 136)(line_width 1))
	)
	(port
		(pt 0 56)
		(input)
		(text "CfgReg[6..0]" (rect 0 0 64 12)(font "Arial" ))
		(text "CfgReg[6..0]" (rect 21 48 85 60)(font "Arial" ))
		(line (pt 0 56)(pt 16 56)(line_width 3))
	)
	(port
		(pt 0 88)
		(input)
		(text "TxReg[7..0]" (rect 0 0 57 12)(font "Arial" ))
		(text "TxReg[7..0]" (rect 21 80 78 92)(font "Arial" ))
		(line (pt 0 88)(pt 16 88)(line_width 3))
	)
	(port
		(pt 0 40)
		(input)
		(text "DIVISOR[16..0]" (rect 0 0 77 12)(font "Arial" ))
		(text "DIVISOR[16..0]" (rect 21 32 98 44)(font "Arial" ))
		(line (pt 0 40)(pt 16 40)(line_width 3))
	)
	(port
		(pt 0 104)
		(input)
		(text "TxSTART" (rect 0 0 46 12)(font "Arial" ))
		(text "TxSTART" (rect 21 96 67 108)(font "Arial" ))
		(line (pt 0 104)(pt 16 104)(line_width 1))
	)
	(port
		(pt 0 120)
		(output)
		(text "TxEND" (rect 32 0 67 12)(font "Arial" ))
		(text "TxEND" (rect 24 112 59 124)(font "Arial" ))
		(line (pt 16 120)(pt 0 120)(line_width 1))
	)
	(port
		(pt 0 72)
		(output)
		(text "TxSTATUS" (rect 32 0 85 12)(font "Arial" ))
		(text "TxSTATUS" (rect 24 64 77 76)(font "Arial" ))
		(line (pt 16 72)(pt 0 72)(line_width 1))
	)
	(port
		(pt 216 64)
		(output)
		(text "TX" (rect 32 0 43 12)(font "Arial" ))
		(text "TX" (rect 184 59 195 71)(font "Arial" ))
		(line (pt 216 64)(pt 200 64)(line_width 1))
	)
	(port
		(pt 216 80)
		(output)
		(text "XOUT[3..0]" (rect 32 0 86 12)(font "Arial" ))
		(text "XOUT[3..0]" (rect 141 75 195 87)(font "Arial" ))
		(line (pt 216 80)(pt 200 80)(line_width 3))
	)
	(drawing
		(rectangle (rect 16 16 200 216)(line_width 1))
	)
)