prev_cmp_basketball.fit.qmsg

cycloneII Quartus verilog开发的简单时序电路

{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { { "Extra Info" "IFSAC_NO_REGISTERS_WERE_PACKED" "" "Extra Info: No registers were packed into other blocks" {  } {  } 1 0 "No registers were packed into other blocks" 0 0 "" 0 0}  } {  } 0 0 "Finished register packing" 0 0 "" 0 0}
{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:00 " "Info: Fitter preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0 0 "Fitter placement operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0 0 "Fitter placement was successful" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "1.837 ns register register " "Info: Estimated most critical path is register to register delay of 1.837 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TimerH\[1\]~reg0 1 REG LAB_X12_Y13 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X12_Y13; Fanout = 4; REG Node = 'TimerH\[1\]~reg0'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { TimerH[1]~reg0 } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.203 ns) + CELL(0.420 ns) 0.623 ns Equal0~42 2 COMB LAB_X12_Y13 3 " "Info: 2: + IC(0.203 ns) + CELL(0.420 ns) = 0.623 ns; Loc. = LAB_X12_Y13; Fanout = 3; COMB Node = 'Equal0~42'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.623 ns" { TimerH[1]~reg0 Equal0~42 } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.145 ns) + CELL(0.420 ns) 1.188 ns Equal0~43 3 COMB LAB_X12_Y13 6 " "Info: 3: + IC(0.145 ns) + CELL(0.420 ns) = 1.188 ns; Loc. = LAB_X12_Y13; Fanout = 6; COMB Node = 'Equal0~43'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { Equal0~42 Equal0~43 } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.145 ns) + CELL(0.420 ns) 1.753 ns TimerL\[0\]~473 4 COMB LAB_X12_Y13 1 " "Info: 4: + IC(0.145 ns) + CELL(0.420 ns) = 1.753 ns; Loc. = LAB_X12_Y13; Fanout = 1; COMB Node = 'TimerL\[0\]~473'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.565 ns" { Equal0~43 TimerL[0]~473 } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 1.837 ns TimerL\[0\]~reg0 5 REG LAB_X12_Y13 6 " "Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 1.837 ns; Loc. = LAB_X12_Y13; Fanout = 6; REG Node = 'TimerL\[0\]~reg0'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { TimerL[0]~473 TimerL[0]~reg0 } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.344 ns ( 73.16 % ) " "Info: Total cell delay = 1.344 ns ( 73.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.493 ns ( 26.84 % ) " "Info: Total interconnect delay = 0.493 ns ( 26.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.837 ns" { TimerH[1]~reg0 Equal0~42 Equal0~43 TimerL[0]~473 TimerL[0]~reg0 } "NODE_NAME" } }  } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0 0 "Fitter routing operations beginning" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "0 X0_Y0 X13_Y14 " "Info: Peak interconnect usage is 0% of the available device resources in the region that extends from location X0_Y0 to location X13_Y14" {  } {  } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 0}  } {  } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" {  } {  } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 0} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" {  } {  } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 0}  } {  } 0 0 "The Fitter performed an Auto Fit compilation.  Optimizations were skipped to reduce compilation time." 0 0 "" 0 0}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "9 " "Warning: Found 9 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerH\[0\] 0 " "Info: Pin \"TimerH\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerH\[1\] 0 " "Info: Pin \"TimerH\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerH\[2\] 0 " "Info: Pin \"TimerH\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerH\[3\] 0 " "Info: Pin \"TimerH\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerL\[0\] 0 " "Info: Pin \"TimerL\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerL\[1\] 0 " "Info: Pin \"TimerL\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerL\[2\] 0 " "Info: Pin \"TimerL\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerL\[3\] 0 " "Info: Pin \"TimerL\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Alarm 0 " "Info: Pin \"Alarm\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." {  } {  } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.fit.smsg " "Info: Generated suppressed messages file E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.fit.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Info" "IQCU_PARALLEL_USED" "1.0 2 2 " "Info: Parallel compilation was enabled and used an average of 1.0 processors and a maximum of 2 processors out of 2 processors allowed" { { "Info" "IQCU_PARALLEL_INSIGNIFICANT_TIME" "" "Info: Less than 1% of process time was spent using more than one processor" {  } {  } 0 0 "Less than 1%% of process time was spent using more than one processor" 0 0 "" 0 0}  } {  } 0 0 "Parallel compilation was enabled and used an average of %1!s! processors and a maximum of %2!i! processors out of %3!i! processors allowed" 0 0 "" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 3 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 3 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "205 " "Info: Peak virtual memory: 205 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Info" "IQEXE_END_BANNER_TIME" "Fri Mar 13 19:08:41 2009 " "Info: Processing ended: Fri Mar 13 19:08:41 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:03 " "Info: Total CPU time (on all processors): 00:00:03" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}