basketball.tan.qmsg

来自「cycloneII Quartus verilog开发的简单时序电路」· QMSG 代码 · 共 17 行 · 第 1/5 页

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 0}
{ "Warning" "WDAT_NO_LOADING_SPECIFIED_ONE_OR_MORE_PINS" "9 " "Warning: Found 9 output pins without output pin load capacitance assignment" { { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerH\[0\] 0 " "Info: Pin \"TimerH\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerH\[1\] 0 " "Info: Pin \"TimerH\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerH\[2\] 0 " "Info: Pin \"TimerH\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerH\[3\] 0 " "Info: Pin \"TimerH\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerL\[0\] 0 " "Info: Pin \"TimerL\[0\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerL\[1\] 0 " "Info: Pin \"TimerL\[1\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerL\[2\] 0 " "Info: Pin \"TimerL\[2\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "TimerL\[3\] 0 " "Info: Pin \"TimerL\[3\]\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0} { "Info" "IDAT_NO_LOADING_SPECIFIED_ON_PIN" "Alarm 0 " "Info: Pin \"Alarm\" has no specified output pin load capacitance -- assuming default load capacitance of 0 pF for timing analysis" {  } {  } 0 0 "Pin \"%1!s!\" has no specified output pin load capacitance -- assuming default load capacitance of %2!d! pF for timing analysis" 0 0 "" 0 0}  } {  } 0 0 "Found %1!d! output pins without output pin load capacitance assignment" 0 0 "" 0 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "CP register TimerL\[1\]~reg0 register TimerH\[2\]~reg0 80.62 ns " "Info: Slack time is 80.62 ns for clock \"CP\" between source register \"TimerL\[1\]~reg0\" and destination register \"TimerH\[2\]~reg0\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "368.6 MHz 2.713 ns " "Info: Fmax is 368.6 MHz (period= 2.713 ns)" {  } {  } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "83.119 ns + Largest register register " "Info: + Largest register to register requirement is 83.119 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "83.333 ns + " "Info: + Setup relationship between source and destination is 83.333 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 83.333 ns " "Info: + Latch edge is 83.333 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination CP 83.333 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"CP\" is 83.333 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source CP 83.333 ns 0.000 ns  50 " "Info: Clock period of Source clock \"CP\" is 83.333 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 0}  } {  } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 0}  } {  } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP destination 2.368 ns + Shortest register " "Info: + Shortest clock path from clock \"CP\" to destination register is 2.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns CP 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'CP'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns CP~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { CP CP~clkctrl } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.537 ns) 2.368 ns TimerH\[2\]~reg0 3 REG LCFF_X12_Y13_N29 5 " "Info: 3: + IC(0.730 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X12_Y13_N29; Fanout = 5; REG Node = 'TimerH\[2\]~reg0'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.267 ns" { CP~clkctrl TimerH[2]~reg0 } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.02 % ) " "Info: Total cell delay = 1.516 ns ( 64.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.852 ns ( 35.98 % ) " "Info: Total interconnect delay = 0.852 ns ( 35.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { CP CP~clkctrl TimerH[2]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { CP {} CP~combout {} CP~clkctrl {} TimerH[2]~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.730ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "CP source 2.368 ns - Longest register " "Info: - Longest clock path from clock \"CP\" to source register is 2.368 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.979 ns) 0.979 ns CP 1 CLK PIN_H2 1 " "Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'CP'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { CP } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.122 ns) + CELL(0.000 ns) 1.101 ns CP~clkctrl 2 COMB CLKCTRL_G2 8 " "Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.122 ns" { CP CP~clkctrl } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 2 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.730 ns) + CELL(0.537 ns) 2.368 ns TimerL\[1\]~reg0 3 REG LCFF_X12_Y13_N11 6 " "Info: 3: + IC(0.730 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X12_Y13_N11; Fanout = 6; REG Node = 'TimerL\[1\]~reg0'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "1.267 ns" { CP~clkctrl TimerL[1]~reg0 } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.516 ns ( 64.02 % ) " "Info: Total cell delay = 1.516 ns ( 64.02 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.852 ns ( 35.98 % ) " "Info: Total interconnect delay = 0.852 ns ( 35.98 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { CP CP~clkctrl TimerL[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { CP {} CP~combout {} CP~clkctrl {} TimerL[1]~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.730ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { CP CP~clkctrl TimerH[2]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { CP {} CP~combout {} CP~clkctrl {} TimerH[2]~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.730ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { CP CP~clkctrl TimerL[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { CP {} CP~combout {} CP~clkctrl {} TimerL[1]~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.730ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.250 ns - " "Info: - Micro clock to output delay of source is 0.250 ns" {  } { { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 14 0 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_TSU_DELAY" "-0.036 ns - " "Info: - Micro setup delay of destination is -0.036 ns" {  } { { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 14 0 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { CP CP~clkctrl TimerH[2]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { CP {} CP~combout {} CP~clkctrl {} TimerH[2]~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.730ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { CP CP~clkctrl TimerL[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { CP {} CP~combout {} CP~clkctrl {} TimerL[1]~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.730ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "2.499 ns - Longest register register " "Info: - Longest register to register delay is 2.499 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns TimerL\[1\]~reg0 1 REG LCFF_X12_Y13_N11 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y13_N11; Fanout = 6; REG Node = 'TimerL\[1\]~reg0'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "" { TimerL[1]~reg0 } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.383 ns) + CELL(0.398 ns) 0.781 ns Equal0~41 2 COMB LCCOMB_X12_Y13_N24 3 " "Info: 2: + IC(0.383 ns) + CELL(0.398 ns) = 0.781 ns; Loc. = LCCOMB_X12_Y13_N24; Fanout = 3; COMB Node = 'Equal0~41'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.781 ns" { TimerL[1]~reg0 Equal0~41 } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.297 ns) + CELL(0.437 ns) 1.515 ns TimerH\[0\]~403 3 COMB LCCOMB_X12_Y13_N8 3 " "Info: 3: + IC(0.297 ns) + CELL(0.437 ns) = 1.515 ns; Loc. = LCCOMB_X12_Y13_N8; Fanout = 3; COMB Node = 'TimerH\[0\]~403'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.734 ns" { Equal0~41 TimerH[0]~403 } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.462 ns) + CELL(0.438 ns) 2.415 ns TimerH\[2\]~406 4 COMB LCCOMB_X12_Y13_N28 1 " "Info: 4: + IC(0.462 ns) + CELL(0.438 ns) = 2.415 ns; Loc. = LCCOMB_X12_Y13_N28; Fanout = 1; COMB Node = 'TimerH\[2\]~406'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.900 ns" { TimerH[0]~403 TimerH[2]~406 } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 14 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.084 ns) 2.499 ns TimerH\[2\]~reg0 5 REG LCFF_X12_Y13_N29 5 " "Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 2.499 ns; Loc. = LCFF_X12_Y13_N29; Fanout = 5; REG Node = 'TimerH\[2\]~reg0'" {  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "0.084 ns" { TimerH[2]~406 TimerH[2]~reg0 } "NODE_NAME" } } { "basketball.v" "" { Text "E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v" 14 0 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.357 ns ( 54.30 % ) " "Info: Total cell delay = 1.357 ns ( 54.30 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.142 ns ( 45.70 % ) " "Info: Total interconnect delay = 1.142 ns ( 45.70 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.499 ns" { TimerL[1]~reg0 Equal0~41 TimerH[0]~403 TimerH[2]~406 TimerH[2]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "2.499 ns" { TimerL[1]~reg0 {} Equal0~41 {} TimerH[0]~403 {} TimerH[2]~406 {} TimerH[2]~reg0 {} } { 0.000ns 0.383ns 0.297ns 0.462ns 0.000ns } { 0.000ns 0.398ns 0.437ns 0.438ns 0.084ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 0}  } { { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { CP CP~clkctrl TimerH[2]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { CP {} CP~combout {} CP~clkctrl {} TimerH[2]~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.730ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.368 ns" { CP CP~clkctrl TimerL[1]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "2.368 ns" { CP {} CP~combout {} CP~clkctrl {} TimerL[1]~reg0 {} } { 0.000ns 0.000ns 0.122ns 0.730ns } { 0.000ns 0.979ns 0.000ns 0.537ns } "" } } { "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/program files/altera/quartus2_8.1/quartus/bin/TimingClosureFloorplan.fld" "" "2.499 ns" { TimerL[1]~reg0 Equal0~41 TimerH[0]~403 TimerH[2]~406 TimerH[2]~reg0 } "NODE_NAME" } } { "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "d:/program files/altera/quartus2_8.1/quartus/bin/Technology_Viewer.qrui" "2.499 ns" { TimerL[1]~reg0 {} Equal0~41 {} TimerH[0]~403 {} TimerH[2]~406 {} TimerH[2]~reg0 {} } { 0.000ns 0.383ns 0.297ns 0.462ns 0.000ns } { 0.000ns 0.398ns 0.437ns 0.438ns 0.084ns } "" } }  } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 0}