basketball.hier_info

cycloneII Quartus verilog开发的简单时序电路

|basketball
TimerH[0] <= TimerH[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TimerH[1] <= TimerH[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TimerH[2] <= TimerH[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TimerH[3] <= TimerH[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TimerL[0] <= TimerL[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TimerL[1] <= TimerL[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TimerL[2] <= TimerL[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
TimerL[3] <= TimerL[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
nRST => TimerH[3]~reg0.ACLR
nRST => TimerH[2]~reg0.ACLR
nRST => TimerH[1]~reg0.PRESET
nRST => TimerH[0]~reg0.PRESET
nRST => TimerL[3]~reg0.ACLR
nRST => TimerL[2]~reg0.ACLR
nRST => TimerL[1]~reg0.ACLR
nRST => TimerL[0]~reg0.ACLR
CP => TimerH[3]~reg0.CLK
CP => TimerH[2]~reg0.CLK
CP => TimerH[1]~reg0.CLK
CP => TimerH[0]~reg0.CLK
CP => TimerL[3]~reg0.CLK
CP => TimerL[2]~reg0.CLK
CP => TimerL[1]~reg0.CLK
CP => TimerL[0]~reg0.CLK
Alarm <= Equal0.DB_MAX_OUTPUT_PORT_TYPE
nPAUSE => TimerL[0]~reg0.ENA
nPAUSE => TimerH[3]~reg0.ENA
nPAUSE => TimerH[2]~reg0.ENA
nPAUSE => TimerH[1]~reg0.ENA
nPAUSE => TimerH[0]~reg0.ENA
nPAUSE => TimerL[3]~reg0.ENA
nPAUSE => TimerL[2]~reg0.ENA
nPAUSE => TimerL[1]~reg0.ENA