basketball.map.rpt

cycloneII Quartus verilog开发的简单时序电路

; HDL message level                                              ; Level2             ; Level2             ;
; Suppress Register Optimization Related Messages                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report       ; 100                ; 100                ;
; Number of Inverted Registers Reported in Synthesis Report      ; 100                ; 100                ;
; Clock MUX Protection                                           ; On                 ; On                 ;
; Auto Gated Clock Conversion                                    ; Off                ; Off                ;
; Block Design Naming                                            ; Auto               ; Auto               ;
; SDC constraint protection                                      ; Off                ; Off                ;
; Synthesis Effort                                               ; Auto               ; Auto               ;
; Allows Asynchronous Clear Usage For Shift Register Replacement ; On                 ; On                 ;
; Analysis & Synthesis Message Level                             ; Medium             ; Medium             ;
+----------------------------------------------------------------+--------------------+--------------------+


+---------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                                                ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path                            ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------+
; basketball.v                     ; yes             ; User Verilog HDL File  ; E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.v ;
+----------------------------------+-----------------+------------------------+---------------------------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 16    ;
;                                             ;       ;
; Total combinational functions               ; 16    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 11    ;
;     -- 3 input functions                    ; 3     ;
;     -- <=2 input functions                  ; 2     ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 16    ;
;     -- arithmetic mode                      ; 0     ;
;                                             ;       ;
; Total registers                             ; 8     ;
;     -- Dedicated logic registers            ; 8     ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 12    ;
; Maximum fan-out node                        ; CP    ;
; Maximum fan-out                             ; 8     ;
; Total fan-out                               ; 90    ;
; Average fan-out                             ; 2.50  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |basketball                ; 16 (16)           ; 8 (8)        ; 0           ; 0            ; 0       ; 0         ; 12   ; 0            ; |basketball         ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 8     ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 8     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; TimerH[0]~reg0                         ; 5       ;
; TimerH[1]~reg0                         ; 4       ;
; Total number of inverted registers = 2 ;         ;
+----------------------------------------+---------+


+------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                           ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
; 3:1                ; 4 bits    ; 8 LEs         ; 4 LEs                ; 4 LEs                  ; Yes        ; |basketball|TimerL[0]~reg0 ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 8.1 Build 163 10/28/2008 SJ Full Version
    Info: Processing started: Fri Mar 13 18:44:04 2009
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off basketball -c basketball
Info: Found 1 design units, including 1 entities, in source file basketball.v
    Info: Found entity 1: basketball
Info: Elaborating entity "basketball" for the top level hierarchy
Info: Registers with preset signals will power-up high
Info: DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back
Info: Implemented 28 device resources after synthesis - the final resource count might be different
    Info: Implemented 3 input pins
    Info: Implemented 9 output pins
    Info: Implemented 16 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 0 warnings
    Info: Peak virtual memory: 166 megabytes
    Info: Processing ended: Fri Mar 13 18:44:05 2009
    Info: Elapsed time: 00:00:01
    Info: Total CPU time (on all processors): 00:00:02