basketball.v.bak

cycloneII Quartus verilog开发的简单时序电路

module basketball(TimerH, TimerL, nRST, CP, Alarm, nPAUSE);
	input nRST, CP, nPAUSE;
	output [3:0]TimerH, TimerL;
	reg [3:0] TimerH, TimerL;
	output Alarm;
	
	assign Alarm = ({TimerH, TimerL} == 8'h00);
	always @(posedge CP or negedge nRST or negedge nPAUSE)
		begin
			if(~nRST)
				{TimerH, TimerL} <= 8'h30;
			else if(~nPAUSE)
				{TimerH, TimerL} <= {TimerH, TimerL};
			else if({TimerH, TimerL} == 8'h00)
				{TimerH, TimerL} <= {TimerH, TimerL};
			else if(TimerL == 4'h0)
				begin
					TimerH <= TimerH - 1'b1;
					TimerL <= 4'h9;
				end
			else
				begin
					TimerH <= TimerH;
					TimerL <= TimerL - 1'b1;
				end
		end
endmodule