basketball.tan.rpt

cycloneII Quartus verilog开发的简单时序电路

                Info: Multicycle Setup factor for Source register is 1
        Info: + Largest clock skew is 0.000 ns
            Info: + Shortest clock path from clock "CP" to destination register is 2.368 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'CP'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
                Info: 3: + IC(0.730 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X12_Y13_N29; Fanout = 5; REG Node = 'TimerH[2]~reg0'
                Info: Total cell delay = 1.516 ns ( 64.02 % )
                Info: Total interconnect delay = 0.852 ns ( 35.98 % )
            Info: - Longest clock path from clock "CP" to source register is 2.368 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'CP'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
                Info: 3: + IC(0.730 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X12_Y13_N11; Fanout = 6; REG Node = 'TimerL[1]~reg0'
                Info: Total cell delay = 1.516 ns ( 64.02 % )
                Info: Total interconnect delay = 0.852 ns ( 35.98 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: - Micro setup delay of destination is -0.036 ns
    Info: - Longest register to register delay is 2.499 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y13_N11; Fanout = 6; REG Node = 'TimerL[1]~reg0'
        Info: 2: + IC(0.383 ns) + CELL(0.398 ns) = 0.781 ns; Loc. = LCCOMB_X12_Y13_N24; Fanout = 3; COMB Node = 'Equal0~41'
        Info: 3: + IC(0.297 ns) + CELL(0.437 ns) = 1.515 ns; Loc. = LCCOMB_X12_Y13_N8; Fanout = 3; COMB Node = 'TimerH[0]~403'
        Info: 4: + IC(0.462 ns) + CELL(0.438 ns) = 2.415 ns; Loc. = LCCOMB_X12_Y13_N28; Fanout = 1; COMB Node = 'TimerH[2]~406'
        Info: 5: + IC(0.000 ns) + CELL(0.084 ns) = 2.499 ns; Loc. = LCFF_X12_Y13_N29; Fanout = 5; REG Node = 'TimerH[2]~reg0'
        Info: Total cell delay = 1.357 ns ( 54.30 % )
        Info: Total interconnect delay = 1.142 ns ( 45.70 % )
Info: Minimum slack time is 391 ps for clock "CP" between source register "TimerH[1]~reg0" and destination register "TimerH[1]~reg0"
    Info: + Shortest register to register delay is 0.407 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y13_N27; Fanout = 4; REG Node = 'TimerH[1]~reg0'
        Info: 2: + IC(0.000 ns) + CELL(0.323 ns) = 0.323 ns; Loc. = LCCOMB_X12_Y13_N26; Fanout = 1; COMB Node = 'TimerH[1]~404'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.407 ns; Loc. = LCFF_X12_Y13_N27; Fanout = 4; REG Node = 'TimerH[1]~reg0'
        Info: Total cell delay = 0.407 ns ( 100.00 % )
    Info: - Smallest register to register requirement is 0.016 ns
        Info: + Hold relationship between source and destination is 0.000 ns
            Info: + Latch edge is 0.000 ns
                Info: Clock period of Destination clock "CP" is 83.333 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Destination register is 1
                Info: Multicycle Hold factor for Destination register is 1
            Info: - Launch edge is 0.000 ns
                Info: Clock period of Source clock "CP" is 83.333 ns with  offset of 0.000 ns and duty cycle of 50
                Info: Multicycle Setup factor for Source register is 1
                Info: Multicycle Hold factor for Source register is 1
        Info: + Smallest clock skew is 0.000 ns
            Info: + Longest clock path from clock "CP" to destination register is 2.368 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'CP'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
                Info: 3: + IC(0.730 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X12_Y13_N27; Fanout = 4; REG Node = 'TimerH[1]~reg0'
                Info: Total cell delay = 1.516 ns ( 64.02 % )
                Info: Total interconnect delay = 0.852 ns ( 35.98 % )
            Info: - Shortest clock path from clock "CP" to source register is 2.368 ns
                Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'CP'
                Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
                Info: 3: + IC(0.730 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X12_Y13_N27; Fanout = 4; REG Node = 'TimerH[1]~reg0'
                Info: Total cell delay = 1.516 ns ( 64.02 % )
                Info: Total interconnect delay = 0.852 ns ( 35.98 % )
        Info: - Micro clock to output delay of source is 0.250 ns
        Info: + Micro hold delay of destination is 0.266 ns
Info: tsu for register "TimerH[3]~reg0" (data pin = "nPAUSE", clock pin = "CP") is 5.168 ns
    Info: + Longest pin to register delay is 7.572 ns
        Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_A5; Fanout = 6; PIN Node = 'nPAUSE'
        Info: 2: + IC(5.338 ns) + CELL(0.420 ns) = 6.588 ns; Loc. = LCCOMB_X12_Y13_N8; Fanout = 3; COMB Node = 'TimerH[0]~403'
        Info: 3: + IC(0.462 ns) + CELL(0.438 ns) = 7.488 ns; Loc. = LCCOMB_X12_Y13_N30; Fanout = 1; COMB Node = 'TimerH[3]~405'
        Info: 4: + IC(0.000 ns) + CELL(0.084 ns) = 7.572 ns; Loc. = LCFF_X12_Y13_N31; Fanout = 4; REG Node = 'TimerH[3]~reg0'
        Info: Total cell delay = 1.772 ns ( 23.40 % )
        Info: Total interconnect delay = 5.800 ns ( 76.60 % )
    Info: + Micro setup delay of destination is -0.036 ns
    Info: - Shortest clock path from clock "CP" to destination register is 2.368 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'CP'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
        Info: 3: + IC(0.730 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X12_Y13_N31; Fanout = 4; REG Node = 'TimerH[3]~reg0'
        Info: Total cell delay = 1.516 ns ( 64.02 % )
        Info: Total interconnect delay = 0.852 ns ( 35.98 % )
Info: tco from clock "CP" to destination pin "Alarm" through register "TimerL[1]~reg0" is 8.047 ns
    Info: + Longest clock path from clock "CP" to source register is 2.368 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'CP'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
        Info: 3: + IC(0.730 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X12_Y13_N11; Fanout = 6; REG Node = 'TimerL[1]~reg0'
        Info: Total cell delay = 1.516 ns ( 64.02 % )
        Info: Total interconnect delay = 0.852 ns ( 35.98 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 5.429 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X12_Y13_N11; Fanout = 6; REG Node = 'TimerL[1]~reg0'
        Info: 2: + IC(0.383 ns) + CELL(0.398 ns) = 0.781 ns; Loc. = LCCOMB_X12_Y13_N24; Fanout = 3; COMB Node = 'Equal0~41'
        Info: 3: + IC(0.283 ns) + CELL(0.275 ns) = 1.339 ns; Loc. = LCCOMB_X12_Y13_N12; Fanout = 6; COMB Node = 'Equal0~43'
        Info: 4: + IC(1.302 ns) + CELL(2.788 ns) = 5.429 ns; Loc. = PIN_A3; Fanout = 0; PIN Node = 'Alarm'
        Info: Total cell delay = 3.461 ns ( 63.75 % )
        Info: Total interconnect delay = 1.968 ns ( 36.25 % )
Info: th for register "TimerL[0]~reg0" (data pin = "nPAUSE", clock pin = "CP") is -4.032 ns
    Info: + Longest clock path from clock "CP" to destination register is 2.368 ns
        Info: 1: + IC(0.000 ns) + CELL(0.979 ns) = 0.979 ns; Loc. = PIN_H2; Fanout = 1; CLK Node = 'CP'
        Info: 2: + IC(0.122 ns) + CELL(0.000 ns) = 1.101 ns; Loc. = CLKCTRL_G2; Fanout = 8; COMB Node = 'CP~clkctrl'
        Info: 3: + IC(0.730 ns) + CELL(0.537 ns) = 2.368 ns; Loc. = LCFF_X12_Y13_N17; Fanout = 6; REG Node = 'TimerL[0]~reg0'
        Info: Total cell delay = 1.516 ns ( 64.02 % )
        Info: Total interconnect delay = 0.852 ns ( 35.98 % )
    Info: + Micro hold delay of destination is 0.266 ns
    Info: - Shortest pin to register delay is 6.666 ns
        Info: 1: + IC(0.000 ns) + CELL(0.830 ns) = 0.830 ns; Loc. = PIN_A5; Fanout = 6; PIN Node = 'nPAUSE'
        Info: 2: + IC(5.332 ns) + CELL(0.420 ns) = 6.582 ns; Loc. = LCCOMB_X12_Y13_N16; Fanout = 1; COMB Node = 'TimerL[0]~473'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 6.666 ns; Loc. = LCFF_X12_Y13_N17; Fanout = 6; REG Node = 'TimerL[0]~reg0'
        Info: Total cell delay = 1.334 ns ( 20.01 % )
        Info: Total interconnect delay = 5.332 ns ( 79.99 % )
Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details.
Warning: Found invalid timing assignments -- see Ignored Timing Assignments report for details
Info: Parallel compilation was enabled and used an average of 1.0 processors and a maximum of 2 processors out of 2 processors allowed
    Info: Less than 1% of process time was spent using more than one processor
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Peak virtual memory: 143 megabytes
    Info: Processing ended: Fri Mar 13 19:08:47 2009
    Info: Elapsed time: 00:00:00
    Info: Total CPU time (on all processors): 00:00:01