📄 basketball.tan.rpt
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Classic Timing Analyzer report for basketball
Fri Mar 13 19:08:47 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Clock Setup: 'CP'
6. Clock Hold: 'CP'
7. tsu
8. tco
9. th
10. Ignored Timing Assignments
11. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2008 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-----------+----------------------------------+----------------------------------+----------------+----------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-----------+----------------------------------+----------------------------------+----------------+----------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 5.168 ns ; nPAUSE ; TimerH[2]~reg0 ; -- ; CP ; 0 ;
; Worst-case tco ; N/A ; None ; 8.047 ns ; TimerL[1]~reg0 ; Alarm ; CP ; -- ; 0 ;
; Worst-case th ; N/A ; None ; -4.032 ns ; nPAUSE ; TimerL[0]~reg0 ; -- ; CP ; 0 ;
; Clock Setup: 'CP' ; 80.620 ns ; 12.00 MHz ( period = 83.333 ns ) ; 368.60 MHz ( period = 2.713 ns ) ; TimerL[1]~reg0 ; TimerH[2]~reg0 ; CP ; CP ; 0 ;
; Clock Hold: 'CP' ; 0.391 ns ; 12.00 MHz ( period = 83.333 ns ) ; N/A ; TimerH[1]~reg0 ; TimerH[1]~reg0 ; CP ; CP ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-----------+----------------------------------+----------------------------------+----------------+----------------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EP2C5F256C6 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Minimum Core Junction Temperature ; 0 ; ; ; ;
; Maximum Core Junction Temperature ; 85 ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; On ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
; Output I/O Timing Endpoint ; Near End ; ; ; ;
; Clock Settings ; CP ; ; CP ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CP ; CP ; User Pin ; 12.0 MHz ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CP' ;
+-----------+-----------------------------------------------+----------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------+-----------------------------------------------+----------------+----------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 80.620 ns ; 368.60 MHz ( period = 2.713 ns ) ; TimerL[1]~reg0 ; TimerH[2]~reg0 ; CP ; CP ; 83.333 ns ; 83.119 ns ; 2.499 ns ;
; 80.620 ns ; 368.60 MHz ( period = 2.713 ns ) ; TimerL[1]~reg0 ; TimerH[3]~reg0 ; CP ; CP ; 83.333 ns ; 83.119 ns ; 2.499 ns ;
; 80.685 ns ; 377.64 MHz ( period = 2.648 ns ) ; TimerL[2]~reg0 ; TimerH[2]~reg0 ; CP ; CP ; 83.333 ns ; 83.119 ns ; 2.434 ns ;
; 80.685 ns ; 377.64 MHz ( period = 2.648 ns ) ; TimerL[2]~reg0 ; TimerH[3]~reg0 ; CP ; CP ; 83.333 ns ; 83.119 ns ; 2.434 ns ;
; 80.776 ns ; 391.08 MHz ( period = 2.557 ns ) ; TimerL[0]~reg0 ; TimerH[2]~reg0 ; CP ; CP ; 83.333 ns ; 83.119 ns ; 2.343 ns ;
; 80.776 ns ; 391.08 MHz ( period = 2.557 ns ) ; TimerL[0]~reg0 ; TimerH[3]~reg0 ; CP ; CP ; 83.333 ns ; 83.119 ns ; 2.343 ns ;
; 80.827 ns ; 399.04 MHz ( period = 2.506 ns ) ; TimerL[1]~reg0 ; TimerH[1]~reg0 ; CP ; CP ; 83.333 ns ; 83.119 ns ; 2.292 ns ;
; 80.834 ns ; 400.16 MHz ( period = 2.499 ns ) ; TimerH[2]~reg0 ; TimerH[2]~reg0 ; CP ; CP ; 83.333 ns ; 83.119 ns ; 2.285 ns ;
; 80.834 ns ; 400.16 MHz ( period = 2.499 ns ) ; TimerH[2]~reg0 ; TimerH[3]~reg0 ; CP ; CP ; 83.333 ns ; 83.119 ns ; 2.285 ns ;
; 80.891 ns ; 409.50 MHz ( period = 2.442 ns ) ; TimerL[3]~reg0 ; TimerH[2]~reg0 ; CP ; CP ; 83.333 ns ; 83.119 ns ; 2.228 ns ;
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