basketball.fit.rpt

cycloneII Quartus verilog开发的简单时序电路

; Optimize Timing for ECOs                                           ; Off                            ; Off                            ;
; Regenerate full fit report during ECO compiles                     ; Off                            ; Off                            ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                  ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                        ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Maximum number of global clocks allowed                            ; -1                             ; -1                             ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+----------------------------------------------+
; Incremental Compilation Preservation Summary ;
+-------------------------+--------------------+
; Type                    ; Value              ;
+-------------------------+--------------------+
; Placement               ;                    ;
;     -- Requested        ; 0 / 36 ( 0.00 % )  ;
;     -- Achieved         ; 0 / 36 ( 0.00 % )  ;
;                         ;                    ;
; Routing (by Connection) ;                    ;
;     -- Requested        ; 0 / 0 ( 0.00 % )   ;
;     -- Achieved         ; 0 / 0 ( 0.00 % )   ;
+-------------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------------------------------------+
; Incremental Compilation Partition Settings                                                                                                       ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
; Partition Name ; Partition Type ; Netlist Type Used ; Preservation Level Used ; Netlist Type Requested ; Preservation Level Requested ; Contents ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+
; Top            ; User-created   ; Source File       ; N/A                     ; Source File            ; N/A                          ;          ;
+----------------+----------------+-------------------+-------------------------+------------------------+------------------------------+----------+


+--------------------------------------------------------------------------------------------+
; Incremental Compilation Placement Preservation                                             ;
+----------------+---------+-------------------+-------------------------+-------------------+
; Partition Name ; # Nodes ; # Preserved Nodes ; Preservation Level Used ; Netlist Type Used ;
+----------------+---------+-------------------+-------------------------+-------------------+
; Top            ; 36      ; 0                 ; N/A                     ; Source File       ;
+----------------+---------+-------------------+-------------------------+-------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/我的程序/Quartus Files/练习8.1 篮球竞赛/basketball.pin.


+--------------------------------------------------------------------+
; Fitter Resource Usage Summary                                      ;
+---------------------------------------------+----------------------+
; Resource                                    ; Usage                ;
+---------------------------------------------+----------------------+
; Total logic elements                        ; 16 / 4,608 ( < 1 % ) ;
;     -- Combinational with no register       ; 8                    ;
;     -- Register only                        ; 0                    ;
;     -- Combinational with a register        ; 8                    ;
;                                             ;                      ;
; Logic element usage by number of LUT inputs ;                      ;
;     -- 4 input functions                    ; 11                   ;
;     -- 3 input functions                    ; 3                    ;
;     -- <=2 input functions                  ; 2                    ;
;     -- Register only                        ; 0                    ;
;                                             ;                      ;
; Logic elements by mode                      ;                      ;
;     -- normal mode                          ; 16                   ;
;     -- arithmetic mode                      ; 0                    ;
;                                             ;                      ;
; Total registers*                            ; 8 / 5,058 ( < 1 % )  ;
;     -- Dedicated logic registers            ; 8 / 4,608 ( < 1 % )  ;
;     -- I/O registers                        ; 0 / 450 ( 0 % )      ;
;                                             ;                      ;
; Total LABs:  partially or completely used   ; 1 / 288 ( < 1 % )    ;
; User inserted logic elements                ; 0                    ;
; Virtual pins                                ; 0                    ;
; I/O pins                                    ; 12 / 158 ( 8 % )     ;
;     -- Clock pins                           ; 1 / 4 ( 25 % )       ;
; Global signals                              ; 1                    ;
; M4Ks                                        ; 0 / 26 ( 0 % )       ;
; Total block memory bits                     ; 0 / 119,808 ( 0 % )  ;