uart_test_stim.pl

Implements a 16550/16750 UART core

    uart_wait  (17);
    uart_read  (IIR, IIR_RLSI | IIR_FE);
    uart_read  (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
    uart_read  (IIR, IIR_CTOI | IIR_FE);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    uart_rrbr  (0x00);
    uart_read  (IIR, IIR_RDAI | IIR_FE);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    uart_write (FCR, FCR_FE | FCR_RXFR);
    uart_wait  (1);
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
    uart_read  (IIR, IIR_THRI | IIR_FE);
    uart_read  (IIR, IIR_NONE | IIR_FE);

    logmessage ("UART: Miscellaneous FIFO tests...");
    uart_write (LCR, 0x03);
    uart_write (IER, IER_ERBI);
    uart_read  (IIR, IIR_NONE | IIR_FE);
    uart_write (FCR, FCR_FE | FCR_RT14);
    uart_read  (IIR, IIR_NONE | IIR_FE);
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
    logmessage ("UART: Sending 8 words");
    uart_send  (8);
    uart_read  (IIR, IIR_NONE | IIR_FE);
    uart_wait  (12);
    uart_read  (IIR, IIR_CTOI | IIR_FE);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    logmessage ("UART: Receiving 8 words");
    uart_recv  (8, 0);
    uart_read  (IIR, IIR_NONE | IIR_FE);
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
    logmessage ("UART: Sending 16 words");
    uart_send  (16);
    uart_wait  (4);
    logmessage ("UART: Receiving 4 words");
    uart_recv  (4, 0);
    logmessage ("UART: Sending 4 words");
    uart_send  (4);
    uart_wait  (12);
    logmessage ("UART: Receiving 12 words");
    uart_recv  (12, 4);
    uart_wait  (8);
    logmessage ("UART: Receiving 2 words");
    uart_recv  (2, 0);
    uart_read  (IIR, IIR_NONE | IIR_FE);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    logmessage ("UART: Sending 40 words");
    uart_send  (40);
    uart_wait  (4);
    uart_read  (LSR, LSR_DR);
    uart_wait  (20);
    uart_read  (LSR, LSR_DR | LSR_OE | LSR_THRE | LSR_TEMT);
    uart_read  (IIR, IIR_CTOI | IIR_FE);
    logmessage ("UART: Receiving 3 words");
    uart_recv  (2, 2);
    uart_rrbr  (0x00);
    uart_read  (IIR, IIR_NONE | IIR_FE);
    logmessage ("UART: Receiving 13 words");
    uart_recv  (13, 1);
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
    uart_read  (IIR, IIR_NONE | IIR_FE);

    logmessage ("UART: Testing FIFO error counter...");
    uart_write (IER, IER_ERBI | IER_ELSI);
    logmessage ("UART: Sending 2 words");
    uart_send  (2);
    uart_wait  (2);
    logmessage ("UART: Sending break");
    uart_write (LCR, $LCR | LCR_BC);
    uart_wait  (1);
    uart_write (LCR, $LCR & ~LCR_BC);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
    logmessage ("UART: Sending 4 words");
    uart_send  (4);
    uart_wait  (4);
    logmessage ("UART: Sending break");
    uart_write (LCR, $LCR | LCR_BC);
    uart_wait  (1);
    uart_write (LCR, $LCR & ~LCR_BC);
    logmessage ("UART: Sending 2 words");
    uart_send  (2);
    uart_wait  (6);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
    uart_read  (IIR, IIR_CTOI | IIR_FE);
    logmessage ("UART: Reading 2 words");
    uart_rrbr  (0x00);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
    uart_rrbr  (0x01);
    uart_wait  (1);
    uart_read  (IIR, IIR_RLSI | IIR_FE);
    uart_read  (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
    logmessage ("UART: Reading break word");
    uart_rrbr  (0x00);
    uart_read  (IIR, IIR_NONE | IIR_FE);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
    logmessage ("UART: Reading 4 words");
    uart_rrbr  (0x00);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
    uart_rrbr  (0x01);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
    uart_rrbr  (0x02);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
    uart_rrbr  (0x03);
    uart_wait  (1);
    uart_read  (IIR, IIR_RLSI | IIR_FE);
    uart_read  (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
    uart_read  (IIR, IIR_NONE | IIR_FE);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
    logmessage ("UART: Reading break word");
    uart_rrbr  (0x00);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    uart_rrbr  (0x00);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    uart_rrbr  (0x01);
    uart_read  (LSR, LSR_THRE | LSR_TEMT);

    logmessage ("UART: Sending break");
    uart_write (LCR, $LCR | LCR_BC);
    uart_wait  (1);
    uart_write (LCR, $LCR & ~LCR_BC);
    uart_read  (IIR, IIR_RLSI | IIR_FE);
    uart_read  (LSR, LSR_DR | LSR_FE | LSR_BI | LSR_THRE | LSR_TEMT | LSR_RXFE);
    uart_read  (IIR, IIR_NONE | IIR_FE);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT | LSR_RXFE);
    logmessage ("UART: Reading break word");
    uart_rrbr  (0x00);
    uart_read  (LSR, LSR_THRE | LSR_TEMT);

    logmessage ("UART: FIFO test end");
}

sub uart_check_fifo64 ()
{
    logmessage ("UART: Testing FIFO in 64 byte mode...");
    uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
    uart_write (FCR, FCR_F64E | FCR_FE | FCR_RXFR | FCR_TXFR);
    uart_read  (IIR, IIR_THRI | IIR_FE);
    uart_write (LCR, $LCR | LCR_DLAB);
    uart_write (FCR, FCR_F64E | FCR_FE);
    uart_write (LCR, $LCR & ~LCR_DLAB);
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);

    uart_read  (LSR, LSR_THRE | LSR_TEMT);
    logmessage ("UART: Testing FIFO trigger level 1 byte...");
    uart_write (FCR, FCR_FE | FCR_RT1);
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);
    uart_send  (1);
    uart_wait  (4);
    uart_read  (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    uart_rrbr  (0x00);
    uart_read  (IIR, IIR_THRI | IIR_FE | IIR_F64E);
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);

    logmessage ("UART: Testing FIFO trigger level 16 byte...");
    uart_write (FCR, FCR_FE | FCR_RT16);
    uart_send  (15);
    uart_wait  (15);
    uart_read  (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    uart_rrbr  (0x00);
    uart_read  (IIR, IIR_THRI | IIR_FE | IIR_F64E);
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);
    uart_send  (3);
    uart_wait  (3);
    uart_read  (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    uart_rrbr  (0x01);
    uart_read  (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
    uart_rrbr  (0x02);
    uart_read  (IIR, IIR_THRI | IIR_FE | IIR_F64E);
    uart_recv  (12, 3);
    uart_recv  (3);
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);

    logmessage ("UART: Testing FIFO trigger level 32 byte...");
    uart_write (FCR, FCR_FE | FCR_RT32);
    uart_send  (31);
    uart_wait  (31);
    uart_read  (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    uart_rrbr  (0x00);
    uart_read  (IIR, IIR_THRI | IIR_FE | IIR_F64E);
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);
    uart_send  (3);
    uart_wait  (3);
    uart_read  (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    uart_rrbr  (0x01);
    uart_read  (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
    uart_rrbr  (0x02);
    uart_read  (IIR, IIR_THRI | IIR_FE | IIR_F64E);
    uart_recv  (28, 3);
    uart_recv  (3);
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);

    logmessage ("UART: Testing FIFO trigger level 56 byte...");
    uart_write (FCR, FCR_FE | FCR_RT56);
    uart_send  (55);
    uart_wait  (55);
    uart_read  (IIR, IIR_CTOI | IIR_FE | IIR_F64E);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    uart_rrbr  (0x00);
    uart_read  (IIR, IIR_THRI | IIR_FE | IIR_F64E);
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);
    uart_send  (3);
    uart_wait  (3);
    uart_read  (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    uart_rrbr  (0x01);
    uart_read  (IIR, IIR_RDAI | IIR_FE | IIR_F64E);
    uart_rrbr  (0x02);
    uart_read  (IIR, IIR_THRI | IIR_FE | IIR_F64E);
    uart_recv  (52, 3);
    uart_recv  (3);
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
    uart_read  (IIR, IIR_NONE | IIR_FE | IIR_F64E);

    uart_write (LCR, $LCR | LCR_DLAB);
    uart_write (FCR, $FCR & ~FCR_F64E);
    uart_write (LCR, $LCR & ~LCR_DLAB);
    uart_read  (IIR, IIR_NONE | IIR_FE);

    logmessage ("UART: FIFO64 test end");
}

sub uart_check_afc ()
{
    logmessage ("UART: Automatic flow control test");
    uart_write (LCR, LCR_WLS8);
    uart_read  (LCR, LCR_WLS8);
    uart_write (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
    uart_read  (IER, IER_ERBI | IER_ETBEI | IER_ELSI | IER_EDSSI);
    logmessage ("UART: Setting FIFO trigger level to 4 bytes");
    uart_write (FCR, FCR_FE | FCR_RT4);
    uart_read  (IIR, IIR_THRI | IIR_FE);
    uart_read  (IIR, IIR_NONE | IIR_FE);
    logmessage ("UART: Enabling Auto-CTS");
    uart_write (MCR, ($MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2)) | MCR_AFE);
    uart_read  (MSR, 0);
    uart_read  (IIR, IIR_NONE | IIR_FE);
    logmessage ("UART: Send 3 words");
    uart_send  (3);
    uart_wait  (6);
    logmessage ("UART: Expecting no data was sent");
    uart_read  (IIR, IIR_NONE | IIR_FE);
    uart_read  (LSR, 0);
    logmessage ("UART: Enabling Auto-RTS");
    uart_write (MCR, $MCR | MCR_RTS);
    logmessage ("UART: Check if CTS is enabled");
    uart_read  (IIR, IIR_NONE | IIR_FE);
    uart_read  (MSR, MSR_DCTS | MSR_CTS);
    uart_wait  (8);
    uart_read  (IIR, IIR_CTOI | IIR_FE);
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    logmessage ("UART: Check if CTS is enabled");
    uart_read  (MSR, MSR_CTS);
    logmessage ("UART: Send 1 word");
    uart_send  (1);
    uart_wait  (2);
    logmessage ("UART: Check if CTS is disabled");
    uart_read  (MSR, MSR_DCTS);
    logmessage ("UART: Check LSR");
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    uart_read  (IIR, IIR_CTOI | IIR_FE);
    logmessage ("UART: Receive 3 words");
    uart_recv  (3);
    logmessage ("UART: Check if CTS is disabled");
    uart_read  (MSR, 0);
    logmessage ("UART: Receive 1 word");
    uart_recv  (1);
    logmessage ("UART: Check LSR");
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
    uart_read  (IIR, IIR_THRI | IIR_FE);
    uart_read  (IIR, IIR_NONE | IIR_FE);
    logmessage ("UART: Check if CTS is enabled again");
    uart_read  (MSR, MSR_DCTS | MSR_CTS);
    logmessage ("UART: Send 6 words");
    uart_send  (5);
    uart_send  (1);
    uart_wait  (4);
    logmessage ("UART: Check if CTS is disabled");
    uart_read  (MSR, MSR_DCTS);
    logmessage ("UART: Check LSR");
    uart_read  (LSR, LSR_DR);
    uart_wait  (1);
    logmessage ("UART: Receive 5 words");
    uart_recv  (5);
    uart_read  (IIR, IIR_NONE | IIR_FE);
    uart_wait  (2);
    logmessage ("UART: Check LSR");
    uart_read  (LSR, LSR_DR | LSR_THRE | LSR_TEMT);
    logmessage ("UART: Check if CTS is enabled again");
    uart_read  (MSR, MSR_DCTS | MSR_CTS);
    logmessage ("UART: Receive 1 words");
    uart_recv  (1);
    logmessage ("UART: Check LSR");
    uart_read  (LSR, LSR_THRE | LSR_TEMT);
    uart_read  (IIR, IIR_THRI | IIR_FE);
    uart_read  (IIR, IIR_NONE | IIR_FE);
    logmessage ("UART: Check if CTS is enabled");
    uart_read  (MSR, MSR_CTS);
    logmessage ("UART: Disable Automatic flow control");
    uart_write (MCR, $MCR & ~(MCR_DTR | MCR_RTS | MCR_OUT1 | MCR_OUT2 | MCR_AFE));
    uart_read  (MSR, MSR_DCTS);
    uart_read  (IIR, IIR_NONE | IIR_FE);
    uart_read  (MCR, $MCR);
    logmessage ("UART: Automatic flow control test finished");
}

if (TEST_CONTROL) {
    uart_check_control_lines ();
}
if (TEST_INTERRUPT) {
    uart_check_interrupt_control ();
}
if (TEST_DEFAULT) {
    uart_check_default ();
}
if (TEST_FIFO) {
    uart_check_fifo ();
}
if (TEST_FIFO64) {
    uart_check_fifo64 ();
}
if (TEST_AFC) {
    uart_check_afc ();
}

##################################################################
# End main process
##################################################################



##################################################################
# Sub functions
##################################################################

# Convert number to binary string
sub num2binary($$)
{
  my($num) = @_;
  my $binary = $num ? '' : '0';    # in case $num is zero
  my $len = $_[1];
  my $result;

  while ($num) {
    $binary .= $num & 1 ? 1 : 0;  # do the LSB
    $num >>= 1;                   # on to the next bit
  }

  $result = scalar reverse $binary;
  while (length($result)<$len) {
    $result = "0".$result;
  }

  return $result;
}


# Insert wait cycles
sub waitcycle($)
{
    printf ("#WAIT %d\n", $_[0]);
    #printf ("DE %d\n", $_[0]+5);
}

# Log message
sub logmessage($)
{
    print "#LOG $_[0]\n";
    #print "LO $_[0]\n";
}

# Read from UART
sub uart_read($$)
{
    printf ("#RD %s %s\n", num2binary ($_[0] & 7, 3), num2binary ($_[1] & 0xFF, 8));
    #printf ("IR 0x%04X 0x%02X\n", UART_ADDRESS + ($_[0] & 7), $_[1] & 0xFF);
}

# Filter read from RBR (mask word length)
sub uart_rrbr($)
{
    my $wls  = $LCR & 0x03;
    my $data = $_[0];

    if ($wls == 0x00) { $data &= 0x1F; }
    if ($wls == 0x01) { $data &= 0x3F; }
    if ($wls == 0x02) { $data &= 0x7F; }
    uart_read (RBR, $data);
}

# Write to UART
sub uart_write($$)
{
    # Shadow register writes to local copy
    SWITCH: {
        if ($_[0] == THR) { $RBR = $_[1]; last SWITCH; }
        if ($_[0] == IER) { $IER = $_[1]; last SWITCH; }
        if ($_[0] == FCR) { $FCR = $_[1]; last SWITCH; }
        if ($_[0] == LCR) { $LCR = $_[1]; last SWITCH; }
        if ($_[0] == MCR) { $MCR = $_[1]; last SWITCH; }
        if ($_[0] == SCR) { $SCR = $_[1]; last SWITCH; }
    }

    printf ("#WR %s %s\n", num2binary ($_[0] & 7, 3), num2binary ($_[1] & 0xFF, 8));
    #printf ("IW 0x%04X 0x%02X\n", UART_ADDRESS + ($_[0] & 7), $_[1] & 0xFF);
}

# Set UART baudrate
sub uart_setbaudrate($)
{
    logmessage ("UART: Setting baudrate to $_[0]");
    $divisor = BAUDGENCLK / (16 * $_[0]);
    uart_write (LCR, $LCR | LCR_DLAB);
    uart_write (DLL, $divisor);
    uart_write (DLM, $divisor >> 8);
    uart_read  (LCR, $LCR);
    uart_read  (DLL, $divisor);
    uart_read  (DLM, $divisor >> 8);
    uart_write (LCR, $LCR & ~LCR_DLAB);
    uart_read  (LCR, $LCR);
}

# Wait until n words are transmitted/received
sub uart_wait ($)
{
    my $steps  = 1;                         # Start bit
       $steps += 5 + ($LCR & 0x03);         # Data
       $steps += $LCR & LCR_PEN ? 1 : 0;    # Parity
       $steps += $LCR & LCR_STB ? 2 : 1;    # Stop bit
       $steps += 2;                         # Extra delay

    my $txtime = $_[0]*$steps*($divisor*16)/BAUDGENCLK;
    waitcycle ($txtime/CYCLE);
}

# Send n bytes
sub uart_send ($)
{
    for (my $i = 0; $i < $_[0]; $i++) {
        uart_write (THR, $i);
        if (!($FCR & FCR_FE)) {
            uart_wait  (1);
        }
    }
}

# Receive n bytes
sub uart_recv ($$)
{
    for (my $i = 0; $i < $_[0]; $i++) {
        uart_rrbr ($i + $_[1]);
    }
}