uart_stim.dat

Implements a 16550/16750 UART core

#WAIT 10
#SET 0 1 1 1 1
#LOG UART: Initializing...
#WR 001 00000000
#WR 010 00000000
#WR 011 00000000
#WR 100 00000000
#WR 111 00000000
#LOG UART: Checking registers after reset...
#RD 000 00000000
#RD 000 00000000
#RD 001 00000000
#RD 010 00000001
#RD 011 00000000
#RD 100 00000000
#RD 101 01100000
#RD 110 00001111
#RD 111 00000000
#LOG UART: Enabling local LOOP mode...
#WR 100 00010000
#RD 100 00010000
#LOG UART: Setting baudrate to 115200
#WR 011 10000000
#WR 000 00000001
#WR 001 00000000
#RD 011 10000000
#RD 000 00000001
#RD 001 00000000
#WR 011 00000000
#RD 011 00000000
#LOG UART: Enabling interrupts...
#WR 001 00001111
#RD 001 00001111
#RD 010 00000010
#RD 010 00000001
#LOG UART: Checking control lines...
#WR 100 00010001
#RD 100 00010001
#RD 010 00000000
#RD 110 00100010
#RD 110 00100000
#RD 010 00000001
#WR 100 00010011
#RD 100 00010011
#RD 010 00000000
#RD 110 00110001
#RD 110 00110000
#RD 010 00000001
#WR 100 00010111
#RD 100 00010111
#RD 110 01110000
#RD 010 00000001
#WR 100 00010011
#RD 100 00010011
#RD 010 00000000
#RD 110 00110100
#RD 010 00000001
#RD 110 00110000
#WR 100 00011011
#RD 100 00011011
#RD 010 00000000
#RD 110 10111000
#RD 110 10110000
#RD 010 00000001
#WR 100 00010000
#RD 100 00010000
#RD 010 00000000
#RD 110 00001011
#RD 010 00000001
#LOG UART: Checking interrupt priority control...
#WR 100 00010001
#WR 100 00010000
#WR 000 00010010
#WAIT 2604
#WR 011 01000000
#WAIT 2604
#WR 011 00000000
#RD 010 00000110
#RD 101 01111011
#RD 010 00000100
#RD 010 00000100
#RD 000 00000000
#WR 000 00110100
#WAIT 2604
#RD 101 01100001
#WR 000 01010110
#RD 010 00000100
#WAIT 2604
#RD 010 00000110
#RD 101 01100011
#RD 101 01100001
#RD 010 00000100
#RD 000 00010110
#RD 010 00000010
#RD 010 00000000
#RD 010 00000000
#RD 110 00000010
#RD 010 00000001
#WR 000 01111000
#WAIT 2604
#RD 010 00000100
#RD 000 00011000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Setting LCR to 0x00
#WR 011 00000000
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 2604
#WR 000 01010101
#WAIT 2604
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 00010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 2604
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 2604
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 2604
#RD 010 00000100
#RD 101 01100001
#RD 000 00001010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01000000
#RD 011 01000000
#WAIT 5208
#RD 010 00000110
#RD 101 01111001
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00000000
#RD 011 00000000
#WAIT 5208
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x01
#WR 011 00000001
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 2893
#WR 000 01010101
#WAIT 2893
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 00010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 2893
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 2893
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00101010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01000001
#RD 011 01000001
#WAIT 5787
#RD 010 00000110
#RD 101 01111001
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00000001
#RD 011 00000001
#WAIT 5787
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x02
#WR 011 00000010
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 3182
#WR 000 01010101
#WAIT 3182
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 01010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 3182
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 3182
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 3182
#RD 010 00000100
#RD 101 01100001
#RD 000 00101010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01000010
#RD 011 01000010
#WAIT 6365
#RD 010 00000110
#RD 101 01111001
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00000010
#RD 011 00000010
#WAIT 6365
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x03
#WR 011 00000011
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 3472
#WR 000 01010101
#WAIT 3472
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 01010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 3472
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 3472
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 3472
#RD 010 00000100
#RD 101 01100001
#RD 000 10101010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01000011
#RD 011 01000011
#WAIT 6944
#RD 010 00000110
#RD 101 01111001
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00000011
#RD 011 00000011
#WAIT 6944
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x04
#WR 011 00000100
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 2893
#WR 000 01010101
#WAIT 2893
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 00010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000001
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000001
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000010
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000010
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000011
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000011
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000100
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000100
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000101
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000101
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000110
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000110
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00000111
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00000111
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001000
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00001000
#RD 010 00000010
#RD 101 01100000
#RD 010 00000001
#WR 000 00001001
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00001001
#RD 010 00000010
#RD 101 01100000
#LOG UART: Transmission test overflow (FIFO disabled)
#WR 000 01010101
#WAIT 2893
#RD 101 01100001
#RD 010 00000100
#WR 000 10101010
#WAIT 2893
#RD 010 00000110
#RD 101 01100011
#RD 010 00000100
#WAIT 2893
#RD 010 00000100
#RD 101 01100001
#RD 000 00001010
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Break control test
#WR 011 01000100
#RD 011 01000100
#WAIT 5787
#RD 010 00000110
#RD 101 01111001
#RD 010 00000100
#RD 101 01100001
#RD 000 00000000
#RD 010 00000001
#RD 101 01100000
#WR 011 00000100
#RD 011 00000100
#WAIT 5787
#RD 101 01100000
#RD 010 00000001
#LOG UART: Setting LCR to 0x05
#WR 011 00000101
#LOG UART: Transmission test single byte (FIFO disabled)
#WAIT 3182
#WR 000 01010101
#WAIT 3182
#RD 101 01100001
#RD 010 00000100
#RD 101 01100001
#RD 000 00010101
#RD 101 01100000
#RD 010 00000010
#RD 010 00000001
#LOG UART: Transmission test multiple bytes (FIFO disabled)
#RD 010 00000001
#WR 000 00000000