uart16750.fit.rpt

Implements a 16550/16750 UART core

; Router Effort Multiplier                                           ; 1.0                            ; 1.0                            ;
; Always Enable Input Buffers                                        ; Off                            ; Off                            ;
; Optimize Hold Timing                                               ; IO Paths and Minimum TPD Paths ; IO Paths and Minimum TPD Paths ;
; Optimize Fast-Corner Timing                                        ; Off                            ; Off                            ;
; PowerPlay Power Optimization                                       ; Normal compilation             ; Normal compilation             ;
; Optimize Timing                                                    ; Normal compilation             ; Normal compilation             ;
; Optimize IOC Register Placement for Timing                         ; On                             ; On                             ;
; Limit to One Fitting Attempt                                       ; Off                            ; Off                            ;
; Final Placement Optimizations                                      ; Automatically                  ; Automatically                  ;
; Fitter Aggressive Routability Optimizations                        ; Automatically                  ; Automatically                  ;
; Fitter Initial Placement Seed                                      ; 1                              ; 1                              ;
; PCI I/O                                                            ; Off                            ; Off                            ;
; Weak Pull-Up Resistor                                              ; Off                            ; Off                            ;
; Enable Bus-Hold Circuitry                                          ; Off                            ; Off                            ;
; Auto Global Memory Control Signals                                 ; Off                            ; Off                            ;
; Auto Packed Registers                                              ; Auto                           ; Auto                           ;
; Auto Delay Chains                                                  ; On                             ; On                             ;
; Auto Merge PLLs                                                    ; On                             ; On                             ;
; Ignore PLL Mode When Merging PLLs                                  ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Fitting     ; Off                            ; Off                            ;
; Perform Physical Synthesis for Combinational Logic for Performance ; Off                            ; Off                            ;
; Perform Register Duplication for Performance                       ; Off                            ; Off                            ;
; Perform Logic to Memory Mapping for Fitting                        ; Off                            ; Off                            ;
; Perform Register Retiming for Performance                          ; Off                            ; Off                            ;
; Perform Asynchronous Signal Pipelining                             ; Off                            ; Off                            ;
; Fitter Effort                                                      ; Auto Fit                       ; Auto Fit                       ;
; Physical Synthesis Effort Level                                    ; Normal                         ; Normal                         ;
; Auto Global Clock                                                  ; On                             ; On                             ;
; Auto Global Register Control Signals                               ; On                             ; On                             ;
; Stop After Congestion Map Generation                               ; Off                            ; Off                            ;
; Save Intermediate Fitting Results                                  ; Off                            ; Off                            ;
; Maximum number of global clocks allowed                            ; -1                             ; -1                             ;
+--------------------------------------------------------------------+--------------------------------+--------------------------------+


+--------------------------------------------------------------------------------------------------------+
; Fitter Partition Preservation Settings                                                                 ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Name ; # Preserved Nodes ; # Nodes ; Preservation Level Requested ; Netlist Type Used      ; Hierarchy ;
+------+-------------------+---------+------------------------------+------------------------+-----------+
; Top  ; 0                 ; 765     ; Placement and Routing        ; Post-Synthesis Netlist ;           ;
+------+-------------------+---------+------------------------------+------------------------+-----------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Netlist Optimizations                                                                                                                                                                                                                                                                            ;
+-------------------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
; Node                    ; Action          ; Operation        ; Reason              ; Node Port ; Node Port Name ; Destination Node                                                                                                                           ; Destination Port ; Destination Port Name ;
+-------------------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+
; uart_16750:inst|iTSR[0] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[0] ; PORTBDATAOUT     ;                       ;
; uart_16750:inst|iTSR[1] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[1] ; PORTBDATAOUT     ;                       ;
; uart_16750:inst|iTSR[2] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[2] ; PORTBDATAOUT     ;                       ;
; uart_16750:inst|iTSR[3] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[3] ; PORTBDATAOUT     ;                       ;
; uart_16750:inst|iTSR[4] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[4] ; PORTBDATAOUT     ;                       ;
; uart_16750:inst|iTSR[5] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[5] ; PORTBDATAOUT     ;                       ;
; uart_16750:inst|iTSR[6] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[6] ; PORTBDATAOUT     ;                       ;
; uart_16750:inst|iTSR[7] ; Packed Register ; Register Packing ; Timing optimization ; REGOUT    ;                ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|altsyncram_t681:FIFOram|q_b[7] ; PORTBDATAOUT     ;                       ;
+-------------------------+-----------------+------------------+---------------------+-----------+----------------+--------------------------------------------------------------------------------------------------------------------------------------------+------------------+-----------------------+


+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in R:/uart16750/syn/Altera/CycloneII/UART16750.pin.


+----------------------------------------------------------------------------+
; Fitter Resource Usage Summary                                              ;
+---------------------------------------------+------------------------------+
; Resource                                    ; Usage                        ;
+---------------------------------------------+------------------------------+
; Total logic elements                        ; 448 / 4,608 ( 10 % )         ;
;     -- Combinational with no register       ; 163                          ;
;     -- Register only                        ; 30                           ;
;     -- Combinational with a register        ; 255                          ;
;                                             ;                              ;
; Logic element usage by number of LUT inputs ;                              ;
;     -- 4 input functions                    ; 223                          ;
;     -- 3 input functions                    ; 72                           ;
;     -- <=2 input functions                  ; 123                          ;
;     -- Register only                        ; 30                           ;
;                                             ;                              ;
; Logic elements by mode                      ;                              ;
;     -- normal mode                          ; 349                          ;
;     -- arithmetic mode                      ; 69                           ;
;                                             ;                              ;
; Total registers*                            ; 285 / 5,058 ( 6 % )          ;
;     -- Dedicated logic registers            ; 285 / 4,608 ( 6 % )          ;
;     -- I/O registers                        ; 0 / 450 ( 0 % )              ;
;                                             ;                              ;
; Total LABs:  partially or completely used   ; 40 / 288 ( 14 % )            ;
; User inserted logic elements                ; 0                            ;
; Virtual pins                                ; 0                            ;
; I/O pins                                    ; 36 / 158 ( 23 % )            ;