uart16750.drc.rpt

来自「Implements a 16550/16750 UART core」· RPT 代码 · 共 217 行 · 第 1/3 页

; Rule A102: Register output should not drive its own control signal directly or through combinational logic                                                                                                                                                                               ; On           ;    ;
; Rule A103: Design should not contain delay chains                                                                                                                                                                                                                                        ; On           ;    ;
; Rule A104: Design should not contain ripple clock structures                                                                                                                                                                                                                             ; On           ;    ;
; Rule A105: Pulses should not be implemented asynchronously                                                                                                                                                                                                                               ; On           ;    ;
; Rule A106: Multiple pulses should not be generated in design                                                                                                                                                                                                                             ; On           ;    ;
; Rule A107: Design should not contain SR latches                                                                                                                                                                                                                                          ; On           ;    ;
; Rule A108: Design should not contain latches                                                                                                                                                                                                                                             ; On           ;    ;
; Rule A109: Combinational logic should not directly drive write enable signal of asynchronous RAM                                                                                                                                                                                         ; On           ;    ;
; Rule A110: Design should not contain asynchronous memory                                                                                                                                                                                                                                 ; On           ;    ;
; Rule S101: Output enable and input of the same tri-state node should not be driven by same signal source                                                                                                                                                                                 ; On           ;    ;
; Rule S102: Synchronous port and asynchronous port of the same register should not be driven by the same signal source                                                                                                                                                                    ; On           ;    ;
; Rule S103: More than one asynchronous signal port of the same register should not be driven by the same signal source                                                                                                                                                                    ; On           ;    ;
; Rule S104: Clock port and any other signal port of same register should not be driven by the same signal source                                                                                                                                                                          ; On           ;    ;
; Rule D101: Data bits are not synchronized when transferred between asynchronous clock domains                                                                                                                                                                                            ; On           ;    ;
; Rule D102: Multiple data bits that are transferred across asynchronous clock domains are synchronized, but not all bits may be aligned in the receiving clock domain                                                                                                                     ; On           ;    ;
; Rule D103: Data bits are not correctly synchronized when transferred between asynchronous clock domains                                                                                                                                                                                  ; On           ;    ;
; Rule H101: Only one VREF pin should be assigned to the HardCopy test pin in an I/O bank (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.) ; On           ;    ;
; Rule H102: PLL clock output drives multiple clock network types (Rule does not apply to all HardCopy and HardCopy Stratix devices. This rule is used to analyze a design only when the rule applies to the design's target HardCopy or HardCopy Stratix device.)                         ; On           ;    ;
; Rule M101: Data bits are not synchronized when transferred to the state machine of asynchronous clock domains                                                                                                                                                                            ; On           ;    ;
; Rule M102: No reset signal defined to initialize the state machine                                                                                                                                                                                                                       ; On           ;    ;
; Rule M103: State machine should not contain an unreachable state                                                                                                                                                                                                                         ; On           ;    ;
; Rule M104: State machine should not contain a deadlock state                                                                                                                                                                                                                             ; On           ;    ;
; Rule M105: State machine should not contain a dead transition                                                                                                                                                                                                                            ; On           ;    ;
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+--------------+----+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Information only Violations                                                                                                                                                                             ;
+------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+---------+
; Rule name                                                        ; Name                                                                                                                       ; Fan-Out ;
+------------------------------------------------------------------+----------------------------------------------------------------------------------------------------------------------------+---------+
; Rule T101: Nodes with more than the specified number of fan-outs ; CLK~clkctrl                                                                                                                ; 288     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; inst1~clkctrl                                                                                                              ; 224     ;
; Rule T101: Nodes with more than the specified number of fan-outs ; ~GND                                                                                                                       ; 34      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; uart_16750:inst|iRXFIFOClear                                                                                               ; 41      ;
; Rule T101: Nodes with more than the specified number of fan-outs ; uart_16750:inst|iFCR_TXFIFOReset                                                                                           ; 33      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; CLK~clkctrl                                                                                                                ; 288     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; inst1~clkctrl                                                                                                              ; 224     ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|iRXFIFOClear                                                                                               ; 41      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; ~GND                                                                                                                       ; 34      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|iFCR_TXFIFOReset                                                                                           ; 33      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|empty_dff      ; 22      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff      ; 17      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|uart_baudgen:UART_BG16|Equal0~179                                                                          ; 17      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; A[1]                                                                                                                       ; 15      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; A[0]                                                                                                                       ; 15      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|Mux0~160                                                                                                   ; 14      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|slib_clock_div:UART_BG2|iQ                                                                                 ; 14      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iQ                                                             ; 14      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|iFCR_FIFOEnable                                                                                            ; 13      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|iRXFIFORead~50                                                                                             ; 13      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|uart_receiver:UART_RX|iDataCountInit                                                                       ; 12      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|State~57                                                                                                   ; 12      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|iLCR[7]                                                                                                    ; 12      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|iA[1]                                                                                                      ; 12      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|uart_receiver:UART_RX|slib_counter:RX_BRC|iCounter[4]                                                      ; 12      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|Mux5~105                                                                                                   ; 12      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_wreq     ; 12      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|iMCR[4]                                                                                                    ; 11      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|uart_receiver:UART_RX|CState.idle                                                                          ; 11      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[0]                                                                        ; 11      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|valid_rreq     ; 11      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[1]                                                                        ; 11      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_wreq~186 ; 11      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|valid_rreq     ; 10      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|iLCR[1]                                                                                                    ; 10      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|uart_receiver:UART_RX|iDataCount[2]                                                                        ; 10      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; A[2]                                                                                                                       ; 10      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|iDIN[0]                                                                                                    ; 10      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|iA[0]                                                                                                      ; 10      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|iTXFIFORead                                                                                                ; 10      ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|iDIN[1]                                                                                                    ; 9       ;
; Rule T102: Top nodes with the highest number of fan-outs         ; uart_16750:inst|iLCR[0]                                                                                                    ; 9       ;