📄 uart16750.tan.rpt
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; 22.962 ns ; 142.03 MHz ( period = 7.041 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.826 ns ;
; 22.982 ns ; 142.43 MHz ( period = 7.021 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.801 ns ;
; 23.031 ns ; 143.43 MHz ( period = 6.972 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.757 ns ;
; 23.033 ns ; 143.47 MHz ( period = 6.970 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.755 ns ;
; 23.053 ns ; 143.88 MHz ( period = 6.950 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.730 ns ;
; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ;
; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ;
; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ;
; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ;
; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ;
; 23.075 ns ; 144.34 MHz ( period = 6.928 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[1] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.663 ns ;
; 23.102 ns ; 144.91 MHz ( period = 6.901 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.686 ns ;
; 23.147 ns ; 145.86 MHz ( period = 6.856 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.641 ns ;
; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ;
; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ;
; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ;
; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg2 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ;
; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg1 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ;
; 23.155 ns ; 146.03 MHz ( period = 6.848 ns ) ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg0 ; uart_16750:inst|iFECounter[0] ; CLK ; CLK ; 30.003 ns ; 29.738 ns ; 6.583 ns ;
; 23.173 ns ; 146.41 MHz ( period = 6.830 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.615 ns ;
; 23.218 ns ; 147.38 MHz ( period = 6.785 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.570 ns ;
; 23.289 ns ; 148.94 MHz ( period = 6.714 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.499 ns ;
; 23.303 ns ; 149.25 MHz ( period = 6.700 ns ) ; uart_16750:inst|iTSR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.485 ns ;
; 23.329 ns ; 149.84 MHz ( period = 6.674 ns ) ; uart_16750:inst|iLCR[0] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.781 ns ; 6.452 ns ;
; 23.360 ns ; 150.53 MHz ( period = 6.643 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.428 ns ;
; 23.416 ns ; 151.81 MHz ( period = 6.587 ns ) ; uart_16750:inst|iTSR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.372 ns ;
; 23.436 ns ; 152.28 MHz ( period = 6.567 ns ) ; uart_16750:inst|iLCR[4] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.347 ns ;
; 23.556 ns ; 155.11 MHz ( period = 6.447 ns ) ; uart_16750:inst|iTSR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.232 ns ;
; 23.616 ns ; 156.57 MHz ( period = 6.387 ns ) ; uart_16750:inst|iLCR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.782 ns ; 6.166 ns ;
; 23.630 ns ; 156.91 MHz ( period = 6.373 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 6.162 ns ;
; 23.648 ns ; 157.36 MHz ( period = 6.355 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 6.144 ns ;
; 23.687 ns ; 158.33 MHz ( period = 6.316 ns ) ; uart_16750:inst|iLCR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.782 ns ; 6.095 ns ;
; 23.695 ns ; 158.53 MHz ( period = 6.308 ns ) ; uart_16750:inst|iTSR[3] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.803 ns ; 6.108 ns ;
; 23.704 ns ; 158.76 MHz ( period = 6.299 ns ) ; uart_16750:inst|iLCR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.079 ns ;
; 23.713 ns ; 158.98 MHz ( period = 6.290 ns ) ; uart_16750:inst|iTSR[4] ; uart_16750:inst|SOUT ; CLK ; CLK ; 30.003 ns ; 29.803 ns ; 6.090 ns ;
; 23.743 ns ; 159.74 MHz ( period = 6.260 ns ) ; uart_16750:inst|iTSR[7] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[0] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 6.045 ns ;
; 23.758 ns ; 160.13 MHz ( period = 6.245 ns ) ; uart_16750:inst|iLCR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2] ; CLK ; CLK ; 30.003 ns ; 29.782 ns ; 6.024 ns ;
; 23.775 ns ; 160.57 MHz ( period = 6.228 ns ) ; uart_16750:inst|iLCR[1] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3] ; CLK ; CLK ; 30.003 ns ; 29.783 ns ; 6.008 ns ;
; 23.796 ns ; 161.11 MHz ( period = 6.207 ns ) ; uart_16750:inst|iTSR[6] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4] ; CLK ; CLK ; 30.003 ns ; 29.788 ns ; 5.992 ns ;
; 23.800 ns ; 161.21 MHz ( period = 6.203 ns ) ; uart_16750:inst|iTSR[2] ; uart_16750:inst|uart_receiver:UART_RX|CState.mwait ; CLK ; CLK ; 30.003 ns ; 29.792 ns ; 5.992 ns ;
; 23.829 ns ; 161.97 MHz ( period = 6.174 ns ) ; uart_16750:inst|iLCR[5] ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1] ; CLK ; CLK ; 30.003 ns ; 29.782 ns ; 5.953 ns ;
; 23.846 ns ; 162.42 MHz ( period = 6.157 ns ) ; uart_16750:inst|iLCR[1] ⌨️ 快捷键说明
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