uart16750.tan.rpt

Implements a 16550/16750 UART core

; Output Pin Load                                                     ; 10                 ;      ; OUT1N   ;             ;
; Output Pin Load                                                     ; 10                 ;      ; OUT2N   ;             ;
; Output Pin Load                                                     ; 10                 ;      ; RTSN    ;             ;
; Output Pin Load                                                     ; 10                 ;      ; DTRN    ;             ;
; Output Pin Load                                                     ; 10                 ;      ; SOUT    ;             ;
; Output Pin Load                                                     ; 10                 ;      ; DOUT[7] ;             ;
; Output Pin Load                                                     ; 10                 ;      ; DOUT[6] ;             ;
; Output Pin Load                                                     ; 10                 ;      ; DOUT[5] ;             ;
; Output Pin Load                                                     ; 10                 ;      ; DOUT[4] ;             ;
; Output Pin Load                                                     ; 10                 ;      ; DOUT[3] ;             ;
; Output Pin Load                                                     ; 10                 ;      ; DOUT[2] ;             ;
; Output Pin Load                                                     ; 10                 ;      ; DOUT[1] ;             ;
; Output Pin Load                                                     ; 10                 ;      ; DOUT[0] ;             ;
+---------------------------------------------------------------------+--------------------+------+---------+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; CLK             ; CLK                ; User Pin ; 33.33 MHz        ; 0.000 ns      ; 0.000 ns     ; --       ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'CLK'                                                                                                                                                                                                                                                                                                                                                                                                                                                                                      ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                                                                                                                                                                ; To                                                                                                                    ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; 22.036 ns                               ; 125.52 MHz ( period = 7.967 ns )                    ; uart_16750:inst|iTSR[3]                                                                                                                                             ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4]                                               ; CLK        ; CLK      ; 30.003 ns                   ; 29.788 ns                 ; 7.752 ns                ;
; 22.054 ns                               ; 125.80 MHz ( period = 7.949 ns )                    ; uart_16750:inst|iTSR[4]                                                                                                                                             ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4]                                               ; CLK        ; CLK      ; 30.003 ns                   ; 29.788 ns                 ; 7.734 ns                ;
; 22.107 ns                               ; 126.65 MHz ( period = 7.896 ns )                    ; uart_16750:inst|iTSR[3]                                                                                                                                             ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3]                                               ; CLK        ; CLK      ; 30.003 ns                   ; 29.788 ns                 ; 7.681 ns                ;
; 22.125 ns                               ; 126.94 MHz ( period = 7.878 ns )                    ; uart_16750:inst|iTSR[4]                                                                                                                                             ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3]                                               ; CLK        ; CLK      ; 30.003 ns                   ; 29.788 ns                 ; 7.663 ns                ;
; 22.178 ns                               ; 127.80 MHz ( period = 7.825 ns )                    ; uart_16750:inst|iTSR[3]                                                                                                                                             ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2]                                               ; CLK        ; CLK      ; 30.003 ns                   ; 29.788 ns                 ; 7.610 ns                ;
; 22.196 ns                               ; 128.09 MHz ( period = 7.807 ns )                    ; uart_16750:inst|iTSR[4]                                                                                                                                             ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2]                                               ; CLK        ; CLK      ; 30.003 ns                   ; 29.788 ns                 ; 7.592 ns                ;
; 22.206 ns                               ; 128.25 MHz ( period = 7.797 ns )                    ; uart_16750:inst|iTSR[2]                                                                                                                                             ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4]                                               ; CLK        ; CLK      ; 30.003 ns                   ; 29.788 ns                 ; 7.582 ns                ;
; 22.249 ns                               ; 128.97 MHz ( period = 7.754 ns )                    ; uart_16750:inst|iTSR[3]                                                                                                                                             ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1]                                               ; CLK        ; CLK      ; 30.003 ns                   ; 29.788 ns                 ; 7.539 ns                ;
; 22.267 ns                               ; 129.27 MHz ( period = 7.736 ns )                    ; uart_16750:inst|iTSR[4]                                                                                                                                             ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[1]                                               ; CLK        ; CLK      ; 30.003 ns                   ; 29.788 ns                 ; 7.521 ns                ;
; 22.277 ns                               ; 129.43 MHz ( period = 7.726 ns )                    ; uart_16750:inst|iTSR[2]                                                                                                                                             ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[3]                                               ; CLK        ; CLK      ; 30.003 ns                   ; 29.788 ns                 ; 7.511 ns                ;
; 22.348 ns                               ; 130.63 MHz ( period = 7.655 ns )                    ; uart_16750:inst|iTSR[2]                                                                                                                                             ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[2]                                               ; CLK        ; CLK      ; 30.003 ns                   ; 29.788 ns                 ; 7.440 ns                ;
; 22.405 ns                               ; 131.61 MHz ( period = 7.598 ns )                    ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; uart_16750:inst|iFECounter[6]                                                                                         ; CLK        ; CLK      ; 30.003 ns                   ; 29.738 ns                 ; 7.333 ns                ;
; 22.405 ns                               ; 131.61 MHz ( period = 7.598 ns )                    ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg4 ; uart_16750:inst|iFECounter[6]                                                                                         ; CLK        ; CLK      ; 30.003 ns                   ; 29.738 ns                 ; 7.333 ns                ;
; 22.405 ns                               ; 131.61 MHz ( period = 7.598 ns )                    ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg3 ; uart_16750:inst|iFECounter[6]                                                                                         ; CLK        ; CLK      ; 30.003 ns                   ; 29.738 ns                 ; 7.333 ns                ;