uart16750.tan.rpt

Implements a 16550/16750 UART core

; Type                         ; Slack     ; Required Time                    ; Actual Time                      ; From                                                                                                                                                                ; To                                                                                                                    ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; 2.580 ns  ; 10.000 ns                        ; 7.420 ns                         ; WR                                                                                                                                                                  ; uart_16750:inst|slib_fifo:UART_TXFF|scfifo:scfifo_component|scfifo_an31:auto_generated|a_dpfifo_te31:dpfifo|empty_dff ; --         ; CLK      ; 0            ;
; Worst-case tco               ; 2.856 ns  ; 15.000 ns                        ; 12.144 ns                        ; uart_16750:inst|slib_fifo:UART_RXFF|scfifo:scfifo_component|scfifo_ko31:auto_generated|a_dpfifo_7g31:dpfifo|altsyncram_h981:FIFOram|ram_block1a0~portb_address_reg5 ; DOUT[3]                                                                                                               ; CLK        ; --       ; 0            ;
; Worst-case tpd               ; N/A       ; None                             ; 14.563 ns                        ; A[1]                                                                                                                                                                ; DOUT[3]                                                                                                               ; --         ; --       ; 0            ;
; Worst-case th                ; N/A       ; None                             ; -2.602 ns                        ; WR                                                                                                                                                                  ; uart_16750:inst|slib_edge_detect:UART_ED_WRITE|iDd                                                                    ; --         ; CLK      ; 0            ;
; Clock Setup: 'CLK'           ; 22.036 ns ; 33.33 MHz ( period = 30.003 ns ) ; 125.52 MHz ( period = 7.967 ns ) ; uart_16750:inst|iTSR[3]                                                                                                                                             ; uart_16750:inst|uart_receiver:UART_RX|slib_mv_filter:RX_MVF|iCounter[4]                                               ; CLK        ; CLK      ; 0            ;
; Clock Hold: 'CLK'            ; 0.391 ns  ; 33.33 MHz ( period = 30.003 ns ) ; N/A                              ; uart_16750:inst|iLSR_FIFOERR                                                                                                                                        ; uart_16750:inst|iLSR_FIFOERR                                                                                          ; CLK        ; CLK      ; 0            ;
; Total number of failed paths ;           ;                                  ;                                  ;                                                                                                                                                                     ;                                                                                                                       ;            ;          ; 0            ;
+------------------------------+-----------+----------------------------------+----------------------------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+-----------------------------------------------------------------------------------------------------------------------+------------+----------+--------------+


+-------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings                                                                                                ;
+---------------------------------------------------------------------+--------------------+------+---------+-------------+
; Option                                                              ; Setting            ; From ; To      ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+---------+-------------+
; Device Name                                                         ; EP2C5F256C6        ;      ;         ;             ;
; Timing Models                                                       ; Final              ;      ;         ;             ;
; Default hold multicycle                                             ; Same as Multicycle ;      ;         ;             ;
; Cut paths between unrelated clock domains                           ; On                 ;      ;         ;             ;
; Cut off read during write signal paths                              ; On                 ;      ;         ;             ;
; Cut off feedback from I/O pins                                      ; On                 ;      ;         ;             ;
; Report Combined Fast/Slow Timing                                    ; Off                ;      ;         ;             ;
; tsu Requirement                                                     ; 10 ns              ;      ;         ;             ;
; tco Requirement                                                     ; 15 ns              ;      ;         ;             ;
; fmax Requirement                                                    ; 33.33 MHz          ;      ;         ;             ;
; Ignore Clock Settings                                               ; Off                ;      ;         ;             ;
; Analyze latches as synchronous elements                             ; On                 ;      ;         ;             ;
; Enable Recovery/Removal analysis                                    ; Off                ;      ;         ;             ;
; Enable Clock Latency                                                ; Off                ;      ;         ;             ;
; Use TimeQuest Timing Analyzer                                       ; Off                ;      ;         ;             ;
; Number of source nodes to report per destination node               ; 10                 ;      ;         ;             ;
; Number of destination nodes to report                               ; 10                 ;      ;         ;             ;
; Number of paths to report                                           ; 200                ;      ;         ;             ;
; Report Minimum Timing Checks                                        ; Off                ;      ;         ;             ;
; Use Fast Timing Models                                              ; Off                ;      ;         ;             ;
; Report IO Paths Separately                                          ; Off                ;      ;         ;             ;
; Perform Multicorner Analysis                                        ; On                 ;      ;         ;             ;
; Reports the worst-case path for each clock domain and analysis      ; Off                ;      ;         ;             ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off                ;      ;         ;             ;
; Clock Settings                                                      ; CLK                ;      ; CLK     ;             ;
; Output Pin Load                                                     ; 10                 ;      ; DDIS    ;             ;
; Output Pin Load                                                     ; 10                 ;      ; INT     ;             ;